Patchwork [U-Boot] ARMV7: OMAP3: Add support for Comelit CPS board

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Submitter Luca Ceresoli
Date March 21, 2011, 11:42 a.m.
Message ID <1300707767-15682-2-git-send-email-luca.ceresoli@comelit.it>
Download mbox | patch
Permalink /patch/87758/
State Superseded
Delegated to: Sandeep Paulraj
Headers show

Comments

Luca Ceresoli - March 21, 2011, 11:42 a.m.
Board support for the Comelit Group SpA CPS board, which is a custom board
based on the BeagleBoard <http://beagleboard.org/> by Texas Instruments.

The board support is based on the BeagleBoard implementation.

Signed-off-by: Luca Ceresoli <luca.ceresoli@comelit.it>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.aribaud@free.fr>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
---
 MAINTAINERS                 |    4 +
 MAKEALL                     |    1 +
 board/comelit/cps/Makefile  |   49 ++++++
 board/comelit/cps/config.mk |   36 ++++
 board/comelit/cps/cps.c     |  173 ++++++++++++++++++++
 board/comelit/cps/cps.h     |  379 +++++++++++++++++++++++++++++++++++++++++++
 boards.cfg                  |    1 +
 include/configs/omap3_cps.h |  315 +++++++++++++++++++++++++++++++++++
 8 files changed, 958 insertions(+), 0 deletions(-)
 create mode 100644 board/comelit/cps/Makefile
 create mode 100644 board/comelit/cps/config.mk
 create mode 100644 board/comelit/cps/cps.c
 create mode 100644 board/comelit/cps/cps.h
 create mode 100644 include/configs/omap3_cps.h
Luca Ceresoli - March 21, 2011, 4:32 p.m.
Wolfgang,

thanks for your patient and prompt review, and sorry for having
overlooked checkpatch.

Il 21/03/2011 12:55, Wolfgang Denk ha scritto:
> Dear Luca Ceresoli,
>
> In message<1300707767-15682-2-git-send-email-luca.ceresoli@comelit.it>  you wrote:
>> Board support for the Comelit Group SpA CPS board, which is a custom board
>> based on the BeagleBoard<http://beagleboard.org/>  by Texas Instruments.
>>
>> The board support is based on the BeagleBoard implementation.
>
> It appears you base this code on an old version of U-Boot.  Please
> update your code base first.

Strange.

My patch is based on current master, on the latest commit that I see
today on git://git.denx.de/u-boot.git:

$ git show HEAD^
commit cc1dd33f273f8c96cbd7539b4a2d1d7aa12773cd
Author: John Schmoller <jschmoller@xes-inc.com>
Date:   Thu Mar 10 16:09:26 2011 -0600

     mpc8[5/6]xx: Ensure POST word does not get reset
...

The "next" branch is much older, and I haven't found any more recent
head in either u-boot-arm nor u-boot-ti.

Where should I rebase my code on?

>
> ALso make sure to run your patch to checkpatch before submitting:
>
> [PATCH] ARMV7: OMAP3: Add support for Comelit CPS board
> total: 4 errors, 325 warnings, 976 lines checked
>
> Please fix these!

Fixed most of them for v2. There are still a few warnings, though, that
I think are false positives:

 > WARNING: Use #include <linux/io.h> instead of <asm/io.h>
 > #169: FILE: board/comelit/cps/cps.c:39:
 > +#include <asm/io.h>

I guess I can safely ignore this one.

 > WARNING: Use of volatile is usually wrong: see 
Documentation/volatile-considered-harmful.txt
 > #1011: FILE: include/configs/omap3_cps.h:305:
 > +extern volatile unsigned int boot_flash_env_addr;

I don't know why it is volatile, but since it's defined this way in
arch/arm/cpu/armv7/omap3/mem.c I think there's a reason.

>
>> --- /dev/null
>> +++ b/board/comelit/cps/config.mk
> ...
>> +CONFIG_SYS_TEXT_BASE = 0x80008000
>
> We don't accept such config.mk files any more.  Please move definition
> into your board config file.

Meaning I should remove config.mk entirely, right?

>
>> +	/* GPIO list
>> +	   - 159 OUT (GPIO5+31): reset for remote camera interface connector.
>> +	   - 19  OUT (GPIO1+19): integrated speaker amplifier (1=on, 0=shdn).
>> +	   - 20  OUT (GPIO1+20): handset amplifier (1=on, 0=shdn).
>> +	*/
>
> Incorrect multiline comment style.

Will fix in v2.

>
> ...
>> --- a/boards.cfg
>> +++ b/boards.cfg
>> @@ -117,6 +117,7 @@ omap3_pandora                arm         armv7       pandora             -
>>   igep0020                     arm         armv7       igep0020            isee           omap3
>>   igep0030                     arm         armv7       igep0030            isee           omap3
>>   am3517_evm                   arm         armv7       am3517evm           logicpd        omap3
>> +omap3_cps                    arm         armv7       cps                 comelit        omap3
>>   omap3_zoom1                  arm         armv7       zoom1               logicpd        omap3
>>   omap3_zoom2                  arm         armv7       zoom2               logicpd        omap3
>>   omap3_beagle                 arm         armv7       beagle              ti             omap3
>
> Please name your board just "cps" (or chose a better name).  There
> shall be no SoC-prefix in the board names.

Will be called dig297 in v2.

>
>> --- /dev/null
>> +++ b/include/configs/omap3_cps.h
>> @@ -0,0 +1,315 @@
> ...
>> +#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
>> +#define CONFIG_OMAP		1	/* in a TI OMAP core */
>> +#define CONFIG_OMAP34XX		1	/* which is a 34XX */
>> +#define CONFIG_OMAP3430		1	/* which is in a 3430 */
>> +#define CONFIG_OMAP3_CPS   	1	/* working with CPS board */
>
> #defines like these which select a feature shall not have values
> assigned.  Remove all these '1' here.  Please fix globally.
>

Ok except for OMAP34XX, since arch/arm/cpu/armv7/start.S at line 114
does:

 > #if (CONFIG_OMAP34XX)

Is it intended?
If that's a mistake, I can submit a trivial patch to fix it.

> Best regards,
>
> Wolfgang Denk
>

Luca
Luca Ceresoli - March 21, 2011, 5:30 p.m.
Il 21/03/2011 17:32, Luca Ceresoli ha scritto:
...
>>> --- a/boards.cfg
>>> +++ b/boards.cfg
>>> @@ -117,6 +117,7 @@ omap3_pandora                arm         armv7       pandora             -
>>>    igep0020                     arm         armv7       igep0020            isee           omap3
>>>    igep0030                     arm         armv7       igep0030            isee           omap3
>>>    am3517_evm                   arm         armv7       am3517evm           logicpd        omap3
>>> +omap3_cps                    arm         armv7       cps                 comelit        omap3
>>>    omap3_zoom1                  arm         armv7       zoom1               logicpd        omap3
>>>    omap3_zoom2                  arm         armv7       zoom2               logicpd        omap3
>>>    omap3_beagle                 arm         armv7       beagle              ti             omap3
>>
>> Please name your board just "cps" (or chose a better name).  There
>> shall be no SoC-prefix in the board names.
>
> Will be called dig297 in v2.

Well, not so fast.

The board is named OMAP3_CPS in the ARM Linux Machine Registry
(http://www.arm.linux.org.uk/developer/machines/list.php?id=2751),
which is reflected in mach-types.h.

I don't know how exactly the registry info is used throughout U-Boot,
and I didn't find documentation about it.

Am I supposed to rename the board in the registry, then wait for
mach-types to be updated in U-Boot before submitting a new patch?

Or can I live with the current name in mach-types and rename elsewhere?

Thanks,
Luca
Wolfgang Denk - March 21, 2011, 6:48 p.m.
Dear Luca Ceresoli,

In message <4D877D80.6060506@comelit.it> you wrote:
> 
> > It appears you base this code on an old version of U-Boot.  Please
> > update your code base first.
> 
> Strange.
> 
> My patch is based on current master, on the latest commit that I see
> today on git://git.denx.de/u-boot.git:

Sorry. I thought we had cleaned up the config.mk file use for these
boards long ago. Seems I was wrong.

>  > WARNING: Use #include <linux/io.h> instead of <asm/io.h>
>  > #169: FILE: board/comelit/cps/cps.c:39:
>  > +#include <asm/io.h>
> 
> I guess I can safely ignore this one.

Yes.

>  > WARNING: Use of volatile is usually wrong: see 
> Documentation/volatile-considered-harmful.txt
>  > #1011: FILE: include/configs/omap3_cps.h:305:
>  > +extern volatile unsigned int boot_flash_env_addr;
> 
> I don't know why it is volatile, but since it's defined this way in
> arch/arm/cpu/armv7/omap3/mem.c I think there's a reason.

No, this should be removed.  See
Documentation/volatile-considered-harmful.txt

> > We don't accept such config.mk files any more.  Please move definition
> > into your board config file.
> 
> Meaning I should remove config.mk entirely, right?

Right.

> > Please name your board just "cps" (or chose a better name).  There
> > shall be no SoC-prefix in the board names.
> 
> Will be called dig297 in v2.

Thanks.

> > #defines like these which select a feature shall not have values
> > assigned.  Remove all these '1' here.  Please fix globally.
> >
> 
> Ok except for OMAP34XX, since arch/arm/cpu/armv7/start.S at line 114
> does:
> 
>  > #if (CONFIG_OMAP34XX)
> 
> Is it intended?
> If that's a mistake, I can submit a trivial patch to fix it.

Ouch.  This is wrong and should be fixed.  Yes, please send a
(separate) patch for that.


Best regards,

Wolfgang Denk
Wolfgang Denk - March 21, 2011, 8:23 p.m.
Dear Luca Ceresoli,

In message <4D878B2C.5050604@comelit.it> you wrote:
>
> > Will be called dig297 in v2.
> 
> Well, not so fast.
> 
> The board is named OMAP3_CPS in the ARM Linux Machine Registry
> (http://www.arm.linux.org.uk/developer/machines/list.php?id=2751),
> which is reflected in mach-types.h.

If you want, you can ask for a name change in the Machine Registry.
On the other hand, I see no inherent issues when the board config name
0n U-Boot (and Linux?) don't match the MACH_ID's name.

But I forgot one thing: it seems also a good idear that the board
config names in U-Boot and Linux match.  But you don't have any Linux
kernel code pushed upstream yet, or have you?


> Am I supposed to rename the board in the registry, then wait for
> mach-types to be updated in U-Boot before submitting a new patch?

No, this is not really necessary.

> Or can I live with the current name in mach-types and rename elsewhere?

Yes.  You may want to clean that up in the near future, but it's not
blocking anything here.

Best regards,

Wolfgang Denk

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 4756f14..8030184 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -599,6 +599,10 @@  Rick Bronson <rick@efn.org>
 
 	AT91RM9200DK	at91rm9200
 
+Luca Ceresoli <luca.ceresoli@comelit.it>
+
+	omap3_cps	ARM ARMV7 (OMAP3530 SoC)
+
 Po-Yu Chuang <ratbert@faraday-tech.com>
 
 	a320evb		FA526 (ARM920T-like) (a320 SoC)
diff --git a/MAKEALL b/MAKEALL
index a732e6a..2e59992 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -425,6 +425,7 @@  LIST_ARMV7="		\
 	igep0030		\
 	mx51evk			\
 	omap3_beagle		\
+	omap3_cps		\
 	omap3_overo		\
 	omap3_evm		\
 	omap3_pandora		\
diff --git a/board/comelit/cps/Makefile b/board/comelit/cps/Makefile
new file mode 100644
index 0000000..fbe2610
--- /dev/null
+++ b/board/comelit/cps/Makefile
@@ -0,0 +1,49 @@ 
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= cps.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/comelit/cps/config.mk b/board/comelit/cps/config.mk
new file mode 100644
index 0000000..e1fcafd
--- /dev/null
+++ b/board/comelit/cps/config.mk
@@ -0,0 +1,36 @@ 
+#
+# (C) Copyright 2011 Comelit Group SpA
+# Luca Ceresoli <luca.ceresoli@comelit.it>
+#
+# Based on board/ti/beagle/config.mk:
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Comelit CPS Board uses OMAP3 (ARM-CortexA8) CPU.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/comelit/cps/cps.c b/board/comelit/cps/cps.c
new file mode 100644
index 0000000..afc5bad
--- /dev/null
+++ b/board/comelit/cps/cps.c
@@ -0,0 +1,173 @@ 
+/*
+ * (C) Copyright 2011 Comelit Group SpA
+ * Luca Ceresoli <luca.ceresoli@comelit.it>
+ *
+ * Based on board/ti/beagle/beagle.c:
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "cps.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET)
+#define NET_LAN9221_RESET_GPIO 12
+static void setup_net_chip(void);
+#endif
+
+#ifdef CONFIG_SMC911X
+/* GPMC CS 5 connected to an SMSC LAN9220 ethernet controller */
+#define NET_LAN9220_GPMC_CONFIG1    0x00001000
+#define NET_LAN9220_GPMC_CONFIG2    0x00080701
+#define NET_LAN9220_GPMC_CONFIG3    0x00020201
+#define NET_LAN9220_GPMC_CONFIG4    0x08010701
+#define NET_LAN9220_GPMC_CONFIG5    0x00061D1D
+#define NET_LAN9220_GPMC_CONFIG6    0x9D030000
+#define NET_LAN9220_GPMC_CONFIG7    0x00000f6c
+#endif
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CPS;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE;
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+
+	twl4030_power_init();
+	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+
+	/* GPIO list
+	   - 159 OUT (GPIO5+31): reset for remote camera interface connector.
+	   - 19  OUT (GPIO1+19): integrated speaker amplifier (1=on, 0=shdn).
+	   - 20  OUT (GPIO1+20): handset amplifier (1=on, 0=shdn).
+	*/
+
+	/* Configure GPIOs to output */
+	writel(~(GPIO19|GPIO20), &gpio1_base->oe);
+	writel(~(GPIO31), &gpio5_base->oe);
+
+	/* Set GPIO values */
+	writel((GPIO19|GPIO20), &gpio1_base->setdataout);
+	writel(0, &gpio5_base->setdataout);
+
+#if defined(CONFIG_CMD_NET)
+	setup_net_chip();
+#endif
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_CPS();
+}
+
+#ifdef CONFIG_CMD_NET
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ *	      Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+#ifdef CONFIG_SMC911X
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+	/* Configure GPMC registers */
+	writel(NET_LAN9220_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
+	writel(NET_LAN9220_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
+	writel(NET_LAN9220_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
+	writel(NET_LAN9220_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
+	writel(NET_LAN9220_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
+	writel(NET_LAN9220_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
+	writel(NET_LAN9220_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
+
+	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+	writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+		&ctrl_base->gpmc_nadv_ale);
+
+	/* Make GPIO 12 as output pin and send a magic pulse through it */
+	if (!omap_request_gpio(NET_LAN9221_RESET_GPIO)) {
+		omap_set_gpio_direction(NET_LAN9221_RESET_GPIO, 0);
+		omap_set_gpio_dataout(NET_LAN9221_RESET_GPIO, 1);
+		udelay(1);
+		omap_set_gpio_dataout(NET_LAN9221_RESET_GPIO, 0);
+		udelay(31000); /* Should be >= 30ms according to datasheet */
+		omap_set_gpio_dataout(NET_LAN9221_RESET_GPIO, 1);
+	}
+#endif /* CONFIG_SMC911X */
+}
+#endif /* CONFIG_CMD_NET */
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/board/comelit/cps/cps.h b/board/comelit/cps/cps.h
new file mode 100644
index 0000000..e9eba20
--- /dev/null
+++ b/board/comelit/cps/cps.h
@@ -0,0 +1,379 @@ 
+/*
+ * (C) Copyright 2011 Comelit Group SpA
+ * Luca Ceresoli <luca.ceresoli@comelit.it>
+ *
+ * Based on board/ti/beagle/beagle.h:
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CPS_H_
+#define _CPS_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"OMAP3 CPS board",
+	"NAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_CPS() \
+/*SDRC*/\
+  MUX_VAL(CP(SDRC_D0),       (IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+  MUX_VAL(CP(SDRC_D1),       (IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+  MUX_VAL(CP(SDRC_D2),       (IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+  MUX_VAL(CP(SDRC_D3),       (IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+  MUX_VAL(CP(SDRC_D4),       (IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+  MUX_VAL(CP(SDRC_D5),       (IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+  MUX_VAL(CP(SDRC_D6),       (IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+  MUX_VAL(CP(SDRC_D7),       (IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+  MUX_VAL(CP(SDRC_D8),       (IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+  MUX_VAL(CP(SDRC_D9),       (IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+  MUX_VAL(CP(SDRC_D10),      (IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+  MUX_VAL(CP(SDRC_D11),      (IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+  MUX_VAL(CP(SDRC_D12),      (IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+  MUX_VAL(CP(SDRC_D13),      (IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+  MUX_VAL(CP(SDRC_D14),      (IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+  MUX_VAL(CP(SDRC_D15),      (IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+  MUX_VAL(CP(SDRC_D16),      (IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+  MUX_VAL(CP(SDRC_D17),      (IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+  MUX_VAL(CP(SDRC_D18),      (IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+  MUX_VAL(CP(SDRC_D19),      (IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+  MUX_VAL(CP(SDRC_D20),      (IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+  MUX_VAL(CP(SDRC_D21),      (IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+  MUX_VAL(CP(SDRC_D22),      (IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+  MUX_VAL(CP(SDRC_D23),      (IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+  MUX_VAL(CP(SDRC_D24),      (IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+  MUX_VAL(CP(SDRC_D25),      (IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+  MUX_VAL(CP(SDRC_D26),      (IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+  MUX_VAL(CP(SDRC_D27),      (IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+  MUX_VAL(CP(SDRC_D28),      (IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+  MUX_VAL(CP(SDRC_D29),      (IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+  MUX_VAL(CP(SDRC_D30),      (IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+  MUX_VAL(CP(SDRC_D31),      (IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+  MUX_VAL(CP(SDRC_CLK),      (IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+  MUX_VAL(CP(SDRC_DQS0),     (IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+  MUX_VAL(CP(SDRC_DQS1),     (IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+  MUX_VAL(CP(SDRC_DQS2),     (IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+  MUX_VAL(CP(SDRC_DQS3),     (IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+  MUX_VAL(CP(SDRC_CKE0),     (IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+  MUX_VAL(CP(SDRC_CKE1),     (IDIS | PTU | DIS | M0)) /*sdrc_cke1: NC*/\
+/*GPMC*/\
+  MUX_VAL(CP(GPMC_A1),       (IDIS | PTU | EN  | M0)) /*GPMC_A1*/\
+  MUX_VAL(CP(GPMC_A2),       (IDIS | PTU | EN  | M0)) /*GPMC_A2*/\
+  MUX_VAL(CP(GPMC_A3),       (IDIS | PTU | EN  | M0)) /*GPMC_A3*/\
+  MUX_VAL(CP(GPMC_A4),       (IDIS | PTU | EN  | M0)) /*GPMC_A4*/\
+  MUX_VAL(CP(GPMC_A5),       (IDIS | PTU | EN  | M0)) /*GPMC_A5*/\
+  MUX_VAL(CP(GPMC_A6),       (IDIS | PTU | EN  | M0)) /*GPMC_A6*/\
+  MUX_VAL(CP(GPMC_A7),       (IDIS | PTU | EN  | M0)) /*GPMC_A7*/\
+  MUX_VAL(CP(GPMC_A8),       (IDIS | PTU | EN  | M0)) /*GPMC_A8*/\
+  MUX_VAL(CP(GPMC_A9),       (IDIS | PTU | EN  | M0)) /*GPMC_A9*/\
+  MUX_VAL(CP(GPMC_A10),      (IDIS | PTU | EN  | M0)) /*GPMC_A10*/\
+  MUX_VAL(CP(GPMC_D0),       (IEN  | PTU | EN  | M0)) /*GPMC_D0*/\
+  MUX_VAL(CP(GPMC_D1),       (IEN  | PTU | EN  | M0)) /*GPMC_D1*/\
+  MUX_VAL(CP(GPMC_D2),       (IEN  | PTU | EN  | M0)) /*GPMC_D2*/\
+  MUX_VAL(CP(GPMC_D3),       (IEN  | PTU | EN  | M0)) /*GPMC_D3*/\
+  MUX_VAL(CP(GPMC_D4),       (IEN  | PTU | EN  | M0)) /*GPMC_D4*/\
+  MUX_VAL(CP(GPMC_D5),       (IEN  | PTU | EN  | M0)) /*GPMC_D5*/\
+  MUX_VAL(CP(GPMC_D6),       (IEN  | PTU | EN  | M0)) /*GPMC_D6*/\
+  MUX_VAL(CP(GPMC_D7),       (IEN  | PTU | EN  | M0)) /*GPMC_D7*/\
+  MUX_VAL(CP(GPMC_D8),       (IEN  | PTU | EN  | M0)) /*GPMC_D8*/\
+  MUX_VAL(CP(GPMC_D9),       (IEN  | PTU | EN  | M0)) /*GPMC_D9*/\
+  MUX_VAL(CP(GPMC_D10),      (IEN  | PTU | EN  | M0)) /*GPMC_D10*/\
+  MUX_VAL(CP(GPMC_D11),      (IEN  | PTU | EN  | M0)) /*GPMC_D11*/\
+  MUX_VAL(CP(GPMC_D12),      (IEN  | PTU | EN  | M0)) /*GPMC_D12*/\
+  MUX_VAL(CP(GPMC_D13),      (IEN  | PTU | EN  | M0)) /*GPMC_D13*/\
+  MUX_VAL(CP(GPMC_D14),      (IEN  | PTU | EN  | M0)) /*GPMC_D14*/\
+  MUX_VAL(CP(GPMC_D15),      (IEN  | PTU | EN  | M0)) /*GPMC_D15*/\
+  MUX_VAL(CP(GPMC_NCS0),     (IDIS | PTU | EN  | M0)) /*GPMC_nCS0: NAND*/\
+  /*GPMC_nCS1/2: not available on CUS package*/\
+  MUX_VAL(CP(GPMC_NCS3),     (IDIS | PTU | DIS | M0)) /*GPMC_nCS3*/\
+  MUX_VAL(CP(GPMC_NCS4),     (IDIS | PTU | DIS | M0)) /*GPMC_nCS4*/\
+  MUX_VAL(CP(GPMC_NCS5),     (IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
+  MUX_VAL(CP(GPMC_NCS6),     (IEN  | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
+  MUX_VAL(CP(GPMC_NCS7),     (IEN  | PTU | EN  | M1)) /*SYS_nDMA_REQ3*/\
+  MUX_VAL(CP(GPMC_NBE1),     (IDIS | PTD | DIS | M0)) /*GPMC_nBE1: NC*/\
+  /*GPMC_WAIT2: not available on CUS package*/\
+  MUX_VAL(CP(GPMC_WAIT3),    (IDIS | PTU | DIS | M0)) /*GPMC_WAIT3: NC*/\
+  MUX_VAL(CP(GPMC_CLK),      (IDIS | PTD | DIS | M0)) /*GPMC_CLK: NC
+    (only asyncronous peripherals are connected)*/ \
+  MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+  MUX_VAL(CP(GPMC_NOE),      (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+  MUX_VAL(CP(GPMC_NWE),      (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+  MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+  MUX_VAL(CP(GPMC_NWP),      (IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+  MUX_VAL(CP(GPMC_WAIT0),    (IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+  /*GPMC_WAIT1: not available on CUS package*/\
+/*DSS*/\
+  MUX_VAL(CP(DSS_PCLK),      (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+  MUX_VAL(CP(DSS_HSYNC),     (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+  MUX_VAL(CP(DSS_VSYNC),     (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+  MUX_VAL(CP(DSS_ACBIAS),    (IDIS | PTU | EN  | M7)) /*DSS_ACBIAS:\
+    AC BIAS: connected to TFT, not to be driven */ \
+  MUX_VAL(CP(DSS_DATA0),     (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+  MUX_VAL(CP(DSS_DATA1),     (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+  MUX_VAL(CP(DSS_DATA2),     (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+  MUX_VAL(CP(DSS_DATA3),     (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+  MUX_VAL(CP(DSS_DATA4),     (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+  MUX_VAL(CP(DSS_DATA5),     (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+  MUX_VAL(CP(DSS_DATA6),     (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+  MUX_VAL(CP(DSS_DATA7),     (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+  MUX_VAL(CP(DSS_DATA8),     (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+  MUX_VAL(CP(DSS_DATA9),     (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+  MUX_VAL(CP(DSS_DATA10),    (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+  MUX_VAL(CP(DSS_DATA11),    (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+  MUX_VAL(CP(DSS_DATA12),    (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+  MUX_VAL(CP(DSS_DATA13),    (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+  MUX_VAL(CP(DSS_DATA14),    (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+  MUX_VAL(CP(DSS_DATA15),    (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+  MUX_VAL(CP(DSS_DATA16),    (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+  MUX_VAL(CP(DSS_DATA17),    (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+  MUX_VAL(CP(DSS_DATA18),    (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+  MUX_VAL(CP(DSS_DATA19),    (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+  MUX_VAL(CP(DSS_DATA20),    (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+  MUX_VAL(CP(DSS_DATA21),    (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+  MUX_VAL(CP(DSS_DATA22),    (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+  MUX_VAL(CP(DSS_DATA23),    (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+/*CAMERA*/\
+  MUX_VAL(CP(CAM_HS),        (IEN  | PTU | EN  | M0)) /*CAM_HS */\
+  MUX_VAL(CP(CAM_VS),        (IEN  | PTU | EN  | M0)) /*CAM_VS */\
+  MUX_VAL(CP(CAM_XCLKA),     (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+  MUX_VAL(CP(CAM_PCLK),      (IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+  MUX_VAL(CP(CAM_FLD),       (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+  MUX_VAL(CP(CAM_D0),        (IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+  MUX_VAL(CP(CAM_D1),        (IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+  MUX_VAL(CP(CAM_D2),        (IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+  MUX_VAL(CP(CAM_D3),        (IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+  MUX_VAL(CP(CAM_D4),        (IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+  MUX_VAL(CP(CAM_D5),        (IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+  MUX_VAL(CP(CAM_D6),        (IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+  MUX_VAL(CP(CAM_D7),        (IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+  MUX_VAL(CP(CAM_D8),        (IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+  MUX_VAL(CP(CAM_D9),        (IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+  MUX_VAL(CP(CAM_D10),       (IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+  MUX_VAL(CP(CAM_D11),       (IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+  MUX_VAL(CP(CAM_XCLKB),     (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+  MUX_VAL(CP(CAM_WEN),       (IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+  MUX_VAL(CP(CAM_STROBE),    (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+  MUX_VAL(CP(CSI2_DX0),      (IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+  MUX_VAL(CP(CSI2_DY0),      (IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+  MUX_VAL(CP(CSI2_DX1),      (IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+  MUX_VAL(CP(CSI2_DY1),      (IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
+/*Audio Interface */\
+  MUX_VAL(CP(MCBSP2_FSX),    (IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+  MUX_VAL(CP(MCBSP2_CLKX),   (IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+  MUX_VAL(CP(MCBSP2_DR),     (IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+  MUX_VAL(CP(MCBSP2_DX),     (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+/*Expansion card */\
+  MUX_VAL(CP(MMC1_CLK),      (IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+  MUX_VAL(CP(MMC1_CMD),      (IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+  MUX_VAL(CP(MMC1_DAT0),     (IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+  MUX_VAL(CP(MMC1_DAT1),     (IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+  MUX_VAL(CP(MMC1_DAT2),     (IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+  MUX_VAL(CP(MMC1_DAT3),     (IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+  MUX_VAL(CP(MMC1_DAT4),     (IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
+  MUX_VAL(CP(MMC1_DAT5),     (IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
+  MUX_VAL(CP(MMC1_DAT6),     (IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
+  MUX_VAL(CP(MMC1_DAT7),     (IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
+/*Wireless LAN */\
+  MUX_VAL(CP(MMC2_CLK),      (IEN  | PTU | EN  | M4)) /*GPIO_130*/\
+  MUX_VAL(CP(MMC2_CMD),      (IEN  | PTU | EN  | M4)) /*GPIO_131*/\
+  MUX_VAL(CP(MMC2_DAT0),     (IEN  | PTU | EN  | M4)) /*GPIO_132*/\
+  MUX_VAL(CP(MMC2_DAT1),     (IEN  | PTU | EN  | M4)) /*GPIO_133*/\
+  MUX_VAL(CP(MMC2_DAT2),     (IEN  | PTU | EN  | M4)) /*GPIO_134*/\
+  MUX_VAL(CP(MMC2_DAT3),     (IEN  | PTU | EN  | M4)) /*GPIO_135*/\
+  MUX_VAL(CP(MMC2_DAT4),     (IEN  | PTU | EN  | M4)) /*GPIO_136*/\
+  MUX_VAL(CP(MMC2_DAT5),     (IEN  | PTU | EN  | M4)) /*GPIO_137*/\
+  MUX_VAL(CP(MMC2_DAT6),     (IEN  | PTU | EN  | M4)) /*GPIO_138*/\
+  MUX_VAL(CP(MMC2_DAT7),     (IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+/*Bluetooth*/\
+  MUX_VAL(CP(MCBSP3_DX),     (IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
+  MUX_VAL(CP(MCBSP3_DR),     (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+  MUX_VAL(CP(MCBSP3_CLKX),   (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+  MUX_VAL(CP(MCBSP3_FSX),    (IEN  | PTD | DIS | M1)) /*UART2_RX*/\
+  MUX_VAL(CP(UART2_CTS),     (IEN  | PTD | DIS | M4)) /*GPIO_144*/\
+  MUX_VAL(CP(UART2_RTS),     (IEN  | PTD | DIS | M4)) /*GPIO_145*/\
+  MUX_VAL(CP(UART2_TX),      (IEN  | PTD | DIS | M4)) /*GPIO_146*/\
+  MUX_VAL(CP(UART2_RX),      (IEN  | PTD | DIS | M4)) /*GPIO_147*/\
+/*Modem Interface */\
+  MUX_VAL(CP(UART1_TX),      (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+  MUX_VAL(CP(UART1_RTS),     (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+  MUX_VAL(CP(UART1_CTS),     (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
+  MUX_VAL(CP(UART1_RX),      (IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+  MUX_VAL(CP(MCBSP4_CLKX),   (IEN  | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
+  MUX_VAL(CP(MCBSP4_DR),     (IEN  | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
+  MUX_VAL(CP(MCBSP4_DX),     (IEN  | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
+  MUX_VAL(CP(MCBSP4_FSX),    (IEN  | PTD | DIS | M1)) /*SSI1_WAKE*/\
+  MUX_VAL(CP(MCBSP_CLKS),    (IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
+/*Serial Interface*/\
+  MUX_VAL(CP(UART3_CTS_RCTX),(IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
+  MUX_VAL(CP(UART3_RX_IRRX), (IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+  MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+  MUX_VAL(CP(HSUSB0_CLK),    (IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+  MUX_VAL(CP(HSUSB0_STP),    (IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+  MUX_VAL(CP(HSUSB0_DIR),    (IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+  MUX_VAL(CP(HSUSB0_NXT),    (IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+  MUX_VAL(CP(HSUSB0_DATA0),  (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+  MUX_VAL(CP(HSUSB0_DATA1),  (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+  MUX_VAL(CP(HSUSB0_DATA2),  (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+  MUX_VAL(CP(HSUSB0_DATA3),  (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+  MUX_VAL(CP(HSUSB0_DATA4),  (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+  MUX_VAL(CP(HSUSB0_DATA5),  (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+  MUX_VAL(CP(HSUSB0_DATA6),  (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+  MUX_VAL(CP(HSUSB0_DATA7),  (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+  MUX_VAL(CP(I2C1_SCL),      (IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+  MUX_VAL(CP(I2C1_SDA),      (IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+  MUX_VAL(CP(I2C2_SCL),      (IEN  | PTU | EN  | M4)) /*GPIO_168*/\
+  MUX_VAL(CP(I2C2_SDA),      (IEN  | PTU | EN  | M4)) /*GPIO_183*/\
+  MUX_VAL(CP(I2C3_SCL),      (IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+  MUX_VAL(CP(I2C3_SDA),      (IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+  MUX_VAL(CP(I2C4_SCL),      (IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+  MUX_VAL(CP(I2C4_SDA),      (IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
+/* USB EHCI (port 2) */\
+  MUX_VAL(CP(ETK_D14_ES2),   (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
+  MUX_VAL(CP(ETK_D15_ES2),   (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
+/* MCSPI1: to TOUCH controller TSC2046 (ADS7846 compatible).*/\
+  MUX_VAL(CP(MCSPI1_CLK),    (IEN  | PTD | EN  | M0)) /*McSPI1_CLK.
+    IEN needed fot the McSPI to "receive" the clock and be able to sample SOMI.
+    See http://e2e.ti.com/support/arm174_microprocessors/omap_applications_processors/f/42/p/29444/102394.aspx#102394 */\
+  MUX_VAL(CP(MCSPI1_SIMO),   (IDIS | PTD | EN  | M0)) /*McSPI1_SIMO*/\
+  MUX_VAL(CP(MCSPI1_SOMI),   (IEN  | PTD | EN  | M0)) /*McSPI1_SOMI*/\
+  MUX_VAL(CP(MCSPI1_CS0),    (IDIS | PTU | EN  | M0)) /*McSPI1_CS0*/\
+/* MCSPI2: verso TFT controller HIMAX.*/\
+  MUX_VAL(CP(MCSPI2_CLK),    (IDIS | PTD | EN  | M0)) /*MCSPI2_CLK*/\
+  MUX_VAL(CP(MCSPI2_SIMO),   (IDIS | PTD | EN  | M0)) /*MCSPI3_SIMO*/\
+  MUX_VAL(CP(MCSPI2_SOMI),   (IDIS | PTU | DIS | M7)) /*MCSPI3_SOMI: NC
+    NC because HIMAX in monodirectional (no SOMI line)*/\
+  MUX_VAL(CP(MCSPI2_CS0),    (IDIS | PTU | EN  | M0)) /*MCSPI3_CS0*/\
+  MUX_VAL(CP(MCSPI2_CS1),    (IDIS | PTU | DIS | M7)) /*Safe mode: NC*/\
+/* GPIO */\
+  MUX_VAL(CP(SYS_BOOT5),     (IEN  | PTD | DIS | M4)) /*GPIO_7: BOOT_ORD*/\
+  MUX_VAL(CP(ETK_CLK_ES2),   (IDIS | PTU | EN  | M4)) /*GPIO_12: ETH_nRST*/\
+  MUX_VAL(CP(ETK_CTL_ES2),   (IEN  | PTU | EN  | M4)) /*GPIO_13: ETH_IRQ*/\
+  MUX_VAL(CP(ETK_D0_ES2),    (IEN  | PTU | DIS | M4)) /*GPIO_14: VDEC_IRQ*/\
+  MUX_VAL(CP(ETK_D1_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_15: VDEC_nPDN*/\
+  MUX_VAL(CP(ETK_D2_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_16: WF_nRESET*/\
+  MUX_VAL(CP(ETK_D3_ES2),    (IEN  | PTU | DIS | M4)) /*GPIO_17: PRES_BORCHIA*/\
+  MUX_VAL(CP(ETK_D4_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_18: TFT_nRES*/\
+  MUX_VAL(CP(ETK_D5_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_19: AMPLI SPK*/\
+  MUX_VAL(CP(ETK_D6_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_20: AMPLI headset*/\
+  MUX_VAL(CP(ETK_D7_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_21: EN_3V3_RADIO*/\
+  MUX_VAL(CP(ETK_D9_ES2),    (IEN  | PTU | DIS | M4)) /*GPIO_23: MMC1_WP*/\
+  MUX_VAL(CP(ETK_D10_ES2),   (IDIS | PTD | EN  | M4)) /*GPIO_24: VDEC_nRESET*/\
+  MUX_VAL(CP(ETK_D11_ES2),   (IDIS | PTD | EN  | M4)) /*GPIO_25: CMD_OUT1 relay borchia*/\
+  MUX_VAL(CP(ETK_D12_ES2),   (IDIS | PTD | EN  | M4)) /*GPIO_26: CMD_OUT2 relay borchia*/\
+  MUX_VAL(CP(ETK_D13_ES2),   (IDIS | PTD | EN  | M4)) /*GPIO_27: CMD_OUT3 relay borchia*/\
+  MUX_VAL(CP(MCBSP1_CLKR),   (IEN  | PTD | DIS | M4)) /*GPIO_156: SW_POS1*/\
+  MUX_VAL(CP(MCBSP1_FSR),    (IEN  | PTU | EN  | M4)) /*GPIO_157: SW_POS2*/\
+  MUX_VAL(CP(MCBSP1_DX),     (IEN  | PTD | DIS | M4)) /*GPIO_158: SW_POS3*/\
+  MUX_VAL(CP(MCBSP1_DR),     (IDIS | PTD | DIS | M4)) /*GPIO_159: nRESET_CAMERA*/\
+  MUX_VAL(CP(MCBSP1_FSX),    (IEN  | PTD | DIS | M4)) /*GPIO_161: HOOK_OFF*/\
+  MUX_VAL(CP(MCBSP1_CLKX),   (IEN  | PTD | DIS | M4)) /*GPIO_162: HOOK_ON*/\
+  MUX_VAL(CP(UART3_RTS_SD),  (IDIS | PTD | EN  | M4)) /*GPIO_164: BT_nRESET*/\
+  MUX_VAL(CP(HDQ_SIO),       (IDIS | PTU | DIS | M4)) /*GPIO_170: NC*/\
+  MUX_VAL(CP(MCSPI1_CS3),    (IEN  | PTU | EN  | M4)) /*GPIO_177: touch pendown*/\
+/*Control and debug */\
+  MUX_VAL(CP(SYS_32K),       (IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+  MUX_VAL(CP(SYS_CLKREQ),    (IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+  MUX_VAL(CP(SYS_NIRQ),      (IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+  MUX_VAL(CP(SYS_BOOT0),     (IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+  MUX_VAL(CP(SYS_BOOT1),     (IEN  | PTD | DIS | M4)) /*GPIO_3*/\
+  MUX_VAL(CP(SYS_BOOT2),     (IEN  | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
+  MUX_VAL(CP(SYS_BOOT3),     (IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+  MUX_VAL(CP(SYS_BOOT4),     (IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+  MUX_VAL(CP(SYS_BOOT6),     (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
+  MUX_VAL(CP(SYS_OFF_MODE),  (IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+  MUX_VAL(CP(SYS_CLKOUT1),   (IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+  MUX_VAL(CP(SYS_CLKOUT2),   (IEN  | PTU | EN  | M4)) /*GPIO_186*/\
+  MUX_VAL(CP(ETK_D8_ES2),    (IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+  MUX_VAL(CP(D2D_MCAD1),     (IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
+  MUX_VAL(CP(D2D_MCAD2),     (IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
+  MUX_VAL(CP(D2D_MCAD3),     (IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
+  MUX_VAL(CP(D2D_MCAD4),     (IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
+  MUX_VAL(CP(D2D_MCAD5),     (IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
+  MUX_VAL(CP(D2D_MCAD6),     (IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
+  MUX_VAL(CP(D2D_MCAD7),     (IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
+  MUX_VAL(CP(D2D_MCAD8),     (IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
+  MUX_VAL(CP(D2D_MCAD9),     (IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
+  MUX_VAL(CP(D2D_MCAD10),    (IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
+  MUX_VAL(CP(D2D_MCAD11),    (IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
+  MUX_VAL(CP(D2D_MCAD12),    (IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
+  MUX_VAL(CP(D2D_MCAD13),    (IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
+  MUX_VAL(CP(D2D_MCAD14),    (IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
+  MUX_VAL(CP(D2D_MCAD15),    (IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
+  MUX_VAL(CP(D2D_MCAD16),    (IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
+  MUX_VAL(CP(D2D_MCAD17),    (IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
+  MUX_VAL(CP(D2D_MCAD18),    (IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
+  MUX_VAL(CP(D2D_MCAD19),    (IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
+  MUX_VAL(CP(D2D_MCAD20),    (IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
+  MUX_VAL(CP(D2D_MCAD21),    (IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
+  MUX_VAL(CP(D2D_MCAD22),    (IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
+  MUX_VAL(CP(D2D_MCAD23),    (IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
+  MUX_VAL(CP(D2D_MCAD24),    (IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
+  MUX_VAL(CP(D2D_MCAD25),    (IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
+  MUX_VAL(CP(D2D_MCAD26),    (IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
+  MUX_VAL(CP(D2D_MCAD27),    (IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
+  MUX_VAL(CP(D2D_MCAD28),    (IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
+  MUX_VAL(CP(D2D_MCAD29),    (IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
+  MUX_VAL(CP(D2D_MCAD30),    (IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
+  MUX_VAL(CP(D2D_MCAD31),    (IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
+  MUX_VAL(CP(D2D_MCAD32),    (IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
+  MUX_VAL(CP(D2D_MCAD33),    (IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
+  MUX_VAL(CP(D2D_MCAD34),    (IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
+  MUX_VAL(CP(D2D_MCAD35),    (IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
+  MUX_VAL(CP(D2D_MCAD36),    (IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
+  MUX_VAL(CP(D2D_CLK26MI),   (IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
+  MUX_VAL(CP(D2D_NRESPWRON), (IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
+  MUX_VAL(CP(D2D_NRESWARM),  (IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
+  MUX_VAL(CP(D2D_ARM9NIRQ),  (IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
+  MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+  MUX_VAL(CP(D2D_SPINT),     (IEN  | PTD | EN  | M0)) /*d2d_spint*/\
+  MUX_VAL(CP(D2D_FRINT),     (IEN  | PTD | EN  | M0)) /*d2d_frint*/\
+  MUX_VAL(CP(D2D_DMAREQ0),   (IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
+  MUX_VAL(CP(D2D_DMAREQ1),   (IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
+  MUX_VAL(CP(D2D_DMAREQ2),   (IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
+  MUX_VAL(CP(D2D_DMAREQ3),   (IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
+  MUX_VAL(CP(D2D_N3GTRST),   (IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+  MUX_VAL(CP(D2D_N3GTDI),    (IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+  MUX_VAL(CP(D2D_N3GTDO),    (IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+  MUX_VAL(CP(D2D_N3GTMS),    (IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
+  MUX_VAL(CP(D2D_N3GTCK),    (IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
+  MUX_VAL(CP(D2D_N3GRTCK),   (IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
+  MUX_VAL(CP(D2D_MSTDBY),    (IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
+  MUX_VAL(CP(D2D_SWAKEUP),   (IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
+  MUX_VAL(CP(D2D_IDLEREQ),   (IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
+  MUX_VAL(CP(D2D_IDLEACK),   (IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
+  MUX_VAL(CP(D2D_MWRITE),    (IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
+  MUX_VAL(CP(D2D_SWRITE),    (IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
+  MUX_VAL(CP(D2D_MREAD),     (IEN  | PTD | DIS | M0)) /*d2d_mread*/\
+  MUX_VAL(CP(D2D_SREAD),     (IEN  | PTD | DIS | M0)) /*d2d_sread*/\
+  MUX_VAL(CP(D2D_MBUSFLAG),  (IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
+  MUX_VAL(CP(D2D_SBUSFLAG),  (IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index 45c3102..62a25a7 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -117,6 +117,7 @@  omap3_pandora                arm         armv7       pandora             -
 igep0020                     arm         armv7       igep0020            isee           omap3
 igep0030                     arm         armv7       igep0030            isee           omap3
 am3517_evm                   arm         armv7       am3517evm           logicpd        omap3
+omap3_cps                    arm         armv7       cps                 comelit        omap3
 omap3_zoom1                  arm         armv7       zoom1               logicpd        omap3
 omap3_zoom2                  arm         armv7       zoom2               logicpd        omap3
 omap3_beagle                 arm         armv7       beagle              ti             omap3
diff --git a/include/configs/omap3_cps.h b/include/configs/omap3_cps.h
new file mode 100644
index 0000000..1b25e99
--- /dev/null
+++ b/include/configs/omap3_cps.h
@@ -0,0 +1,315 @@ 
+/*
+ * (C) Copyright 2011 Comelit Group SpA
+ * Luca Ceresoli <luca.ceresoli@comelit.it>
+ *
+ * Based on omap3_beagle.h:
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the OMAP3530 CPS board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3430		1	/* which is in a 3430 */
+#define CONFIG_OMAP3_CPS   	1	/* working with CPS board */
+
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ				/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+						/* Sector */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10) /* 1 MB (UBI requires >= 512 kB) */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration: UART3 (ttyO2)
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR		1
+
+/* library portions to compile in */
+#define CONFIG_RBTREE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_UBI		/* UBI Support			*/
+#define CONFIG_CMD_UBIFS	/* UBIFS Support		*/
+#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands    */
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:896k(uboot)ro,"\
+                        	"128k(uboot-env)ro,3m(kernel)ro,252m(ubi)"
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#undef CONFIG_CMD_NFS		/* NFS support			*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C			1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER		1
+#define CONFIG_TWL4030_LED		1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+
+#if defined(CONFIG_CMD_NET)
+/*
+ * SMSC9220 Ethernet
+ */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X		1
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE     0x2C000000
+
+#endif /* (CONFIG_CMD_NET) */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY		1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyO2,115200n8\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=nand0,3\0"\
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"nandroot=ubi0:rootfs ro\0" \
+	"nandrootfstype=ubifs\0" \
+	"nfspath=/srv/nfs\0" \
+	"tftpfilename=uImage\0" \
+	"gatewayip=0.0.0.0\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${mtdparts} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype} " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${mtdparts} " \
+		"ubi.mtd=3 " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype} " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"${mtdparts} " \
+		"root=/dev/nfs rw " \
+		"nfsroot=${serverip}:${nfspath} " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 100000 300000; " \
+ 		"bootm ${loadaddr}\0" \
+	"netboot=echo Booting from network ...; " \
+		"run netargs; " \
+		"tftp ${loadaddr} ${serverip}:${tftpfilename}; " \
+		"bootm ${loadaddr}\0" \
+	"resetenv=nand erase e0000 20000\0"\
+
+#define CONFIG_BOOTCOMMAND \
+	"run nandboot"
+
+#define CONFIG_AUTO_COMPLETE		1
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"CPS# "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
+								/* works on */
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
+							/* load address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE		boot_flash_base
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_IS_IN_NAND		1
+#define SMNAND_ENV_OFFSET		0x0E0000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
+#define CONFIG_ENV_OFFSET		boot_flash_off
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+#ifndef __ASSEMBLY__
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */