Patchwork [U-Boot,v3,15/23] km_arm: change some register values for SDRAM initialization

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Submitter Heiko Schocher
Date March 21, 2011, 7:02 a.m.
Message ID <1300690939-31511-16-git-send-email-hs@denx.de>
Download mbox | patch
Permalink /patch/87711/
State Superseded
Headers show

Comments

Heiko Schocher - March 21, 2011, 7:02 a.m.
These new values were given by Clive Stubbings from Xentech.
According to him they should be used on all bobcat designs.

The changes are the following:
- enables UART0 and UART1 pins in MPP
- define some L2 cache settings
- changes a SDRAM timing to better fit the hardware
- removed three writes that were the same as the reset values

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
Changes for v2:
  - nothing
Changes for v3:
  - nothing

 board/keymile/km_arm/kwbimage.cfg |   32 ++++++++++++++++++--------------
 1 files changed, 18 insertions(+), 14 deletions(-)

Patch

diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg
index 26d6aa0..b2f5193 100644
--- a/board/keymile/km_arm/kwbimage.cfg
+++ b/board/keymile/km_arm/kwbimage.cfg
@@ -27,16 +27,18 @@ 
 # Boot Media configurations
 BOOT_FROM	spi	# Boot from SPI flash
 
-DATA 0xFFD10000 0x01111111	# MPP Control 0 Register
-# bit 3-0:   MPPSel0	1, NF_IO[2]
-# bit 7-4:   MPPSel1	1, NF_IO[3]
-# bit 12-8:  MPPSel2	1, NF_IO[4]
-# bit 15-12: MPPSel3	1, NF_IO[5]
+DATA 0xFFD10000 0x01112222	# MPP Control 0 Register
+# bit 3-0:   MPPSel0	2, NF_IO[2]
+# bit 7-4:   MPPSel1	2, NF_IO[3]
+# bit 12-8:  MPPSel2	2, NF_IO[4]
+# bit 15-12: MPPSel3	2, NF_IO[5]
 # bit 19-16: MPPSel4	1, NF_IO[6]
 # bit 23-20: MPPSel5	1, NF_IO[7]
 # bit 27-24: MPPSel6	1, SYSRST_O
 # bit 31-28: MPPSel7	0, GPO[7]
 
+DATA 0xFFD10004 0x03303300
+
 DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
 # bit 3-0:   MPPSel16	0, GPIO[16]
 # bit 7-4:   MPPSel17	0, GPIO[17]
@@ -48,8 +50,8 @@  DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
 # bit 31-28: MPPSel23	0, GPIO[23]
 
 DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
-DATA 0xFFD20134 0xBBBBBBBB	# L2 RAM Timing 0 Register
-DATA 0xFFD20138 0x00BBBBBB	# L2 RAM Timing 1 Register
+DATA 0xFFD20134 0x66666666	# L2 RAM Timing 0 Register
+DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
 DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
 DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
 DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
@@ -63,7 +65,7 @@  DATA 0xFFD01400 0x43000400	# SDRAM Configuration Register
 # bit29-26: zero
 # bit31-30: 01
 
-DATA 0xFFD01404 0x36343000	# DDR Controller Control Low
+DATA 0xFFD01404 0x39543000	# DDR Controller Control Low
 # bit 3-0:  0 reserved
 # bit 4:    0=addr/cmd in smame cycle
 # bit 5:    0=clk is driven during self refresh, we don't care for APX
@@ -75,7 +77,7 @@  DATA 0xFFD01404 0x36343000	# DDR Controller Control Low
 # bit30-28: 3 required
 # bit31:    0=no additional STARTBURST delay
 
-DATA 0xFFD01408 0x2302544B	# DDR Timing (Low) (active cycles value +1)
+DATA 0xFFD01408 0x34136552	# DDR Timing (Low) (active cycles value +1)
 # bit3-0:   TRAS lsbs
 # bit7-4:   TRCD
 # bit11- 8: TRP
@@ -86,7 +88,7 @@  DATA 0xFFD01408 0x2302544B	# DDR Timing (Low) (active cycles value +1)
 # bit27-24: TRRD
 # bit31-28: TRTP
 
-DATA 0xFFD0140C 0x00000032	#  DDR Timing (High)
+DATA 0xFFD0140C 0x00000033	#  DDR Timing (High)
 # bit6-0:   TRFC
 # bit8-7:   TR2R
 # bit10-9:  TR2W
@@ -116,8 +118,8 @@  DATA 0xFFD01418 0x00000000	#  DDR Operation
 # bit3-0:   0x0, DDR cmd
 # bit31-4:  0 required
 
-DATA 0xFFD0141C 0x00000642	#  DDR Mode
-DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+DATA 0xFFD0141C 0x00000652	#  DDR Mode
+DATA 0xFFD01420 0x00000044	#  DDR Extended Mode
 # bit0:    0,  DDR DLL enabled
 # bit1:    0,  DDR drive strenght normal
 # bit2:    1,  DDR ODT control lsd disabled
@@ -140,6 +142,8 @@  DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
 # bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
 # bit15-12: 1111 required
 # bit31-16: 0    required
+DATA 0xFFD01428 0x00074510
+DATA 0xFFD0147c 0x00007451
 
 DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
 DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
@@ -153,7 +157,7 @@  DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
 DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
 DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
 
-DATA 0xFFD01494 0x00000000	#  DDR ODT Control (Low)
+DATA 0xFFD01494 0x00010001	#  DDR ODT Control (Low)
 # bit3-0:  0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
 # bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
 
@@ -162,7 +166,7 @@  DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
 # bit3-2:  00, ODT1 controlled by register
 # bit31-4: zero, required
 
-DATA 0xFFD0149C 0x0000E90F	# CPU ODT Control
+DATA 0xFFD0149C 0x0000FC11	# CPU ODT Control
 # bit3-0:  F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
 # bit7-4:  0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
 # bit9-8:  1, ODTEn, never active