[v6,01/23] RISC-V Maintainers

Message ID	1519344729-73482-2-git-send-email-mjc@sifive.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Michael Clark <mjc@sifive.com> To: qemu-devel@nongnu.org Date: Fri, 23 Feb 2018 13:11:47 +1300 Message-Id: <1519344729-73482-2-git-send-email-mjc@sifive.com> In-Reply-To: <1519344729-73482-1-git-send-email-mjc@sifive.com> References: <1519344729-73482-1-git-send-email-mjc@sifive.com> Subject: [Qemu-devel] [PATCH v6 01/23] RISC-V Maintainers Precedence: list Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, RISC-V Patches <patches@groups.riscv.org> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	RISC-V QEMU Port Submission \| expand [v6,00/23] RISC-V QEMU Port Submission [v6,01/23] RISC-V Maintainers [v6,02/23] RISC-V ELF Machine Definition [v6,03/23] RISC-V CPU Core Definition [v6,04/23] RISC-V Disassembler [v6,05/23] RISC-V CPU Helpers [v6,06/23] RISC-V FPU Support [v6,07/23] RISC-V GDB Stub [v6,08/23] RISC-V TCG Code Generation [v6,09/23] RISC-V Physical Memory Protection [v6,10/23] RISC-V Linux User Emulation [v6,11/23] Add symbol table callback function interface to load_elf [v6,12/23] RISC-V HTIF Console [v6,13/23] RISC-V HART Array [v6,14/23] SiFive RISC-V CLINT Block [v6,15/23] SiFive RISC-V PLIC Block [v6,16/23] RISC-V Spike Machines [v6,17/23] RISC-V VirtIO Machine [v6,18/23] SiFive RISC-V UART Device [v6,19/23] SiFive RISC-V PRCI Block [v6,20/23] SiFive RISC-V Test Finisher [v6,21/23] SiFive Freedom E300 RISC-V Machine [v6,22/23] SiFive Freedom U500 RISC-V Machine [v6,23/23] RISC-V Build Infrastructure

Message ID

1519344729-73482-2-git-send-email-mjc@sifive.com

State

New

Headers

From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Date: Fri, 23 Feb 2018 13:11:47 +1300
Message-Id: <1519344729-73482-2-git-send-email-mjc@sifive.com>
In-Reply-To: <1519344729-73482-1-git-send-email-mjc@sifive.com>
References: <1519344729-73482-1-git-send-email-mjc@sifive.com>
Subject: [Qemu-devel] [PATCH v6 01/23] RISC-V Maintainers
Precedence: list
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	RISC-V Patches <patches@groups.riscv.org>
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

RISC-V QEMU Port Submission | expand

Commit Message

Michael Clark Feb. 23, 2018, 12:11 a.m. UTC

Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian
Koppelmann as RISC-V Maintainers.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
---
 MAINTAINERS | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 6e7adad..147b05f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -233,6 +233,17 @@  F: hw/ppc/
 F: include/hw/ppc/
 F: disas/ppc.c
 
+RISC-V
+M: Michael Clark <mjc@sifive.com>
+M: Palmer Dabbelt <palmer@sifive.com>
+M: Sagar Karandikar <sagark@eecs.berkeley.edu>
+M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
+S: Maintained
+F: target/riscv/
+F: hw/riscv/
+F: include/hw/riscv/
+F: disas/riscv.c
+
 S390
 M: Richard Henderson <rth@twiddle.net>
 M: Alexander Graf <agraf@suse.de>