Patchwork [U-Boot,3/4] powerpc/mpc8xxx: disable rcw_en bit for non-DDR3

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Submitter Kumar Gala
Date March 17, 2011, 8:58 p.m.
Message ID <1300395492-21155-3-git-send-email-galak@kernel.crashing.org>
Download mbox | patch
Permalink /patch/87429/
State Accepted
Commit 4ca31929466b2804eac74d04ec7bf656c568250e
Delegated to: Kumar Gala
Headers show

Comments

Kumar Gala - March 17, 2011, 8:58 p.m.
From: York Sun <yorksun@freescale.com>

rcw_en bit is only available for DDR3 controllers. It is a reserved bit on
DDR1 and DDR2 controllers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)
Kumar Gala - March 23, 2011, 5:22 a.m.
On Mar 17, 2011, at 3:58 PM, Kumar Gala wrote:

> From: York Sun <yorksun@freescale.com>
> 
> rcw_en bit is only available for DDR3 controllers. It is a reserved bit on
> DDR1 and DDR2 controllers.
> 
> Signed-off-by: York Sun <yorksun@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |    2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)

applied

- k

Patch

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 8ef6ca8..cefabe7 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -682,7 +682,9 @@  static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 		| ((obc_cfg & 0x1) << 6)
 		| ((ap_en & 0x1) << 5)
 		| ((d_init & 0x1) << 4)
+#ifdef CONFIG_FSL_DDR3
 		| ((rcw_en & 0x1) << 2)
+#endif
 		| ((md_en & 0x1) << 0)
 		);
 	debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);