[rs6000] (v2) PR84220 remove RS6000_BTI_NOT_OPAQUE refs from builtins table

Message ID 1518565208.11602.332.camel@brimstone.rchland.ibm.com
State New
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  • [rs6000] (v2) PR84220 remove RS6000_BTI_NOT_OPAQUE refs from builtins table
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Commit Message

Will Schmidt Feb. 13, 2018, 11:40 p.m.
Hi,
This is (v2), which is notably more comprehensive than (v1).
  Some of our builtin definitions were allowing invalid parameters, and a
subsequent ICE (on invalid code) were the result.  This is due to the use of
RS6000_BTI_NOT_OPAQUE (which allowed vector arguments), where a
RS6000_BTI_INTSI appears to be a more appropriate choice.
This change adjusts the definitions for the VEC_SLD, VEC_SLDW, vec_XXSLDWI
and VEC_XXPERMDI entries.
    
Testcases have been added to ensure we generate the 'invalid intrinsic'
message as is appropriate, instead of ICEing.
Giving credit, this was found by Peter Bergner while working another issue.
    
Sniff-tests passed on P8.  Doing larger reg-test across power systems now.
OK for trunk?
Thanks,
-Will
    
[gcc]
    
2018-02-13  Will Schmidt  <will_schmidt@vnet.ibm.com>
    
	PR target/84220
	* config/rs6000/rs6000-c.c: Update definitions for
	ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VEC_SLDW,
	VSX_BUILTIN_VEC_XXSLDWI, and ALTIVEC_BUILTIN_VEC_XXPERMDI builtins.
    
[testsuite]

2018-02-13  Will Schmidt  <will_schmidt@vnet.ibm.com>

	PR target/84220
	* gcc.target/powerpc/pr84220-sld.c: New test.
	* gcc.target/powerpc/pr84220-sld2.c: New test.
	* gcc.target/powerpc/pr84220-sldw.c: New test.
	* gcc.target/powerpc/pr84220-xxperm.c: New test.
	* gcc.target/powerpc/pr84220-xxsld.c: New test.

Comments

Segher Boessenkool Feb. 14, 2018, 10:53 a.m. | #1
Hi!

On Tue, Feb 13, 2018 at 05:40:08PM -0600, Will Schmidt wrote:
>   Some of our builtin definitions were allowing invalid parameters, and a
> subsequent ICE (on invalid code) were the result.  This is due to the use of
> RS6000_BTI_NOT_OPAQUE (which allowed vector arguments), where a
> RS6000_BTI_INTSI appears to be a more appropriate choice.
> This change adjusts the definitions for the VEC_SLD, VEC_SLDW, vec_XXSLDWI
> and VEC_XXPERMDI entries.

> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr84220-xxperm.c
> @@ -0,0 +1,100 @@
> +/* PR target/84220 */
> +/* Test to ensure we generate invalid parameter errors rather than an ICE
> +    when calling vec_xxpermdi() with invalid parameters.  */
> +/* { dg-do compile { target { powerpc64*-*-* } } } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mvsx" } */

Does this test need powerpc64*?  Or does it need lp64 instead, or nothing?

Looks good, please look at that detail again; okay for trunk.  Thanks!


Segher
Will Schmidt Feb. 14, 2018, 3:34 p.m. | #2
On Wed, 2018-02-14 at 04:53 -0600, Segher Boessenkool wrote:
> Hi!
> 
> On Tue, Feb 13, 2018 at 05:40:08PM -0600, Will Schmidt wrote:
> >   Some of our builtin definitions were allowing invalid parameters, and a
> > subsequent ICE (on invalid code) were the result.  This is due to the use of
> > RS6000_BTI_NOT_OPAQUE (which allowed vector arguments), where a
> > RS6000_BTI_INTSI appears to be a more appropriate choice.
> > This change adjusts the definitions for the VEC_SLD, VEC_SLDW, vec_XXSLDWI
> > and VEC_XXPERMDI entries.
> 
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/powerpc/pr84220-xxperm.c
> > @@ -0,0 +1,100 @@
> > +/* PR target/84220 */
> > +/* Test to ensure we generate invalid parameter errors rather than an ICE
> > +    when calling vec_xxpermdi() with invalid parameters.  */
> > +/* { dg-do compile { target { powerpc64*-*-* } } } */
> > +/* { dg-require-effective-target powerpc_vsx_ok } */
> > +/* { dg-options "-O2 -mvsx" } */
> 
> Does this test need powerpc64*?  Or does it need lp64 instead, or nothing?

Good catch.  :-)   slightly more coverage when removing the target.
Changed it to just a dg-do compile stanza to match the other tests.

Thanks,
-Will

> Looks good, please look at that detail again; okay for trunk.  Thanks!
> 
> 
> Segher
>

Patch

diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index a68be51..843a375 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -3654,64 +3654,65 @@  const struct altivec_builtin_types altivec_overloaded_builtins[] = {
   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF,
-    RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
-    RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
-    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
-    RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
-    RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
-    RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
-    RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
-    RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
-    RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
-    RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
-    RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF,
-    RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
-    RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
-    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
-    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
 
   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
-    RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
-    RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
-    RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
-    RS6000_BTI_unsigned_V8HI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
-    RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
-    RS6000_BTI_unsigned_V4SI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
-    RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_INTSI },
   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
-    RS6000_BTI_unsigned_V2DI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI },
+
   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
@@ -4152,57 +4153,58 @@  const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     ~RS6000_BTI_unsigned_V16QI },
   { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI,
     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
     ~RS6000_BTI_UINTQI },
   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
-    RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
-    RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
-    RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
-    RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
-    RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
-    RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
-    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
-    RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF,
-    RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF,
-    RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
+
   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF,
-    RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
-    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
-    RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF,
-    RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
-    RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
-    RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
-    RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
-    RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
-    RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI },
   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
-    RS6000_BTI_NOT_OPAQUE },
+    RS6000_BTI_INTSI },
 
   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
diff --git a/gcc/testsuite/gcc.target/powerpc/pr84220-sld.c b/gcc/testsuite/gcc.target/powerpc/pr84220-sld.c
new file mode 100644
index 0000000..2536fc3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr84220-sld.c
@@ -0,0 +1,97 @@ 
+/* PR target/84220 */
+/* Test to ensure we generate invalid parameter errors rather than an ICE
+    when calling builtin_vec_sld() with invalid parameters.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+typedef vector bool char vbc_t;
+typedef vector signed char vsc_t;
+typedef vector unsigned char vuc_t;
+typedef vector bool int vbi_t;
+typedef vector signed int vsi_t;
+typedef vector unsigned int vui_t;
+typedef vector pixel vp_t;
+typedef vector bool short vbs_t;
+typedef vector signed short vss_t;
+typedef vector unsigned short vus_t;
+typedef vector float vf_t;
+
+void 
+test_vbc ( vbc_t v1, vbc_t v2, vbc_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vsc ( vsc_t v1, vsc_t v2, vsc_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vuc ( vuc_t v1, vuc_t v2, vuc_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vbi ( vbi_t v1, vbi_t v2, vbi_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vsi ( vsi_t v1, vsi_t v2, vsi_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vui ( vui_t v1, vui_t v2, vui_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vp ( vp_t v1, vp_t v2, vp_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vbs ( vbs_t v1, vbs_t v2, vbs_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vss ( vss_t v1, vss_t v2, vss_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vus ( vus_t v1, vus_t v2, vus_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vf ( vf_t v1, vf_t v2, vf_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr84220-sld2.c b/gcc/testsuite/gcc.target/powerpc/pr84220-sld2.c
new file mode 100644
index 0000000..5e973e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr84220-sld2.c
@@ -0,0 +1,41 @@ 
+/* PR target/84220 */
+/* Test to ensure we generate invalid parameter errors rather than an ICE
+    when calling builtin_vec_sld() with invalid parameters.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-maltivec -mpower8-vector" } */
+
+#include <altivec.h>
+
+typedef  vector  bool long long vbl_t;
+typedef  vector  signed long long vsl_t;
+typedef  vector  unsigned long long vul_t;
+typedef  vector  double vd_t;
+
+void 
+test_vbl ( vbl_t v1, vbl_t v2, vbl_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vsl ( vsl_t v1, vsl_t v2, vsl_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vul ( vul_t v1, vul_t v2, vul_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
+
+void 
+test_vd ( vd_t v1, vd_t v2, vd_t v3 )  \
+{
+  __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  __builtin_vec_sld(v1, v2, 3);
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr84220-sldw.c b/gcc/testsuite/gcc.target/powerpc/pr84220-sldw.c
new file mode 100644
index 0000000..a3b4be6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr84220-sldw.c
@@ -0,0 +1,80 @@ 
+/* PR target/84220 */
+/* Test to ensure we generate invalid parameter errors rather than an ICE
+    when calling builtin_vec_sldw() with invalid parameters.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx" } */
+
+#include <altivec.h>
+
+typedef  vector bool char vbc_t;
+typedef  vector  signed char vsc_t;
+typedef  vector  unsigned char vuc_t;
+typedef  vector  bool int vbi_t;
+typedef  vector  signed int vsi_t;
+typedef  vector  unsigned int vui_t;
+typedef  vector  pixel vp_t;
+typedef  vector  bool short vbs_t;
+typedef  vector  signed short vss_t;
+typedef  vector  unsigned short vus_t;
+typedef  vector  float vf_t;
+typedef  vector  bool long long vbl_t;
+typedef  vector  signed long long vsl_t;
+typedef  vector  unsigned long long vul_t;
+typedef  vector  double vd_t;
+
+void 
+test_vsc ( vsc_t v1, vsc_t v2, vsc_t v3 )  \
+{
+  vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vec_sldw(v1, v2, 3);
+}
+
+void 
+test_vuc ( vuc_t v1, vuc_t v2, vuc_t v3 )  \
+{
+  vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vec_sldw(v1, v2, 3);
+}
+
+void 
+test_vsi ( vsi_t v1, vsi_t v2, vsi_t v3 )  \
+{
+  vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vec_sldw(v1, v2, 3);
+}
+
+void 
+test_vui ( vui_t v1, vui_t v2, vui_t v3 )  \
+{
+  vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vec_sldw(v1, v2, 3);
+}
+
+void 
+test_vsl ( vsl_t v1, vsl_t v2, vsl_t v3 )  \
+{
+  vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vec_sldw(v1, v2, 3);
+}
+
+void 
+test_vul ( vul_t v1, vul_t v2, vul_t v3 )  \
+{
+  vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vec_sldw(v1, v2, 3);
+}
+
+void 
+test_vss ( vss_t v1, vss_t v2, vss_t v3 )  \
+{
+  vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vec_sldw(v1, v2, 3);
+}
+
+void 
+test_vus ( vus_t v1, vus_t v2, vus_t v3 )  \
+{
+  vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vec_sldw(v1, v2, 3);
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr84220-xxperm.c b/gcc/testsuite/gcc.target/powerpc/pr84220-xxperm.c
new file mode 100644
index 0000000..b0ae6d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr84220-xxperm.c
@@ -0,0 +1,100 @@ 
+/* PR target/84220 */
+/* Test to ensure we generate invalid parameter errors rather than an ICE
+    when calling vec_xxpermdi() with invalid parameters.  */
+/* { dg-do compile { target { powerpc64*-*-* } } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+#include <altivec.h>
+void abort (void);
+
+vector double vdx = { 0.0, 1.0 };
+vector double vdy = { 2.0, 3.0 };
+vector double vdz;
+
+vector signed long long vsllx = { 0, 1 };
+vector signed long long vslly = { 2, 3 };
+vector signed long long vsllz;
+
+vector unsigned long long vullx = { 0, 1 };
+vector unsigned long long vully = { 2, 3 };
+vector unsigned long long vullz;
+
+vector float vfx = { 0.0, 1.0, 2.0, 3.0 };
+vector float vfy = { 4.0, 5.0, 6.0, 7.0 };
+vector float vfz;
+
+vector signed int vsix = { 0, 1, 2, 3 };
+vector signed int vsiy = { 4, 5, 6, 7 };
+vector signed int vsiz;
+
+vector unsigned int vuix = { 0, 1, 2, 3 };
+vector unsigned int vuiy = { 4, 5, 6, 7 };
+vector unsigned int vuiz;
+
+vector signed short vssx = { 0, 1, 2, 3, 4, 5, 6, 7 };
+vector signed short vssy = { 8, 9, 10, 11, 12, 13, 14, 15 };
+vector signed short vssz;
+
+vector unsigned short vusx = { 0, 1, 2, 3, 4, 5, 6, 7 };
+vector unsigned short vusy = { 8, 9, 10, 11, 12, 13, 14, 15 };
+vector unsigned short vusz;
+
+vector signed char vscx = { 0, 1, 2, 3, 4, 5, 6, 7,
+			    8, 9, 10, 11, 12, 13, 14, 15 };
+vector signed char vscy = { 16, 17, 18, 19, 20, 21, 22, 23,
+			    24, 25, 26, 27, 28, 29, 30, 31 };
+vector signed char vscz;
+
+vector unsigned char vucx = { 0, 1, 2, 3, 4, 5, 6, 7,
+			    8, 9, 10, 11, 12, 13, 14, 15 };
+vector unsigned char vucy = { 16, 17, 18, 19, 20, 21, 22, 23,
+			    24, 25, 26, 27, 28, 29, 30, 31 };
+vector unsigned char vucz;
+
+int
+main ()
+{
+  vdz = vec_xxpermdi (vdx, vdy, 0b01);
+  if (vdz[0] != 0.0 || vdz[1] != 3.0)
+    abort ();
+  vdz = vec_xxpermdi (vdx, vdy, vscx); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vsllz = vec_xxpermdi (vsllx, vslly, 0b10);
+  vsllz = vec_xxpermdi (vsllx, vslly, vslly); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vullz = vec_xxpermdi (vullx, vully, 0b10);
+  vullz = vec_xxpermdi (vullx, vully, vully); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  if (vsllz[0] != 1 || vsllz[1] != 2)
+    abort ();
+
+  vfz = vec_xxpermdi (vfx, vfy, 0b01);
+  vfz = vec_xxpermdi (vfx, vfy, vfy); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  if (vfz[0] != 0.0 || vfz[1] != 1.0 || vfz[2] != 6.0 || vfz[3] != 7.0)
+    abort ();
+
+  vsiz = vec_xxpermdi (vsix, vsiy, 0b10);
+  vsiz = vec_xxpermdi (vsix, vsiy, vsiy); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vuiz = vec_xxpermdi (vuix, vuiy, 0b10);
+  vuiz = vec_xxpermdi (vuix, vuiy, vuiy); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  if (vsiz[0] != 2 || vsiz[1] != 3 || vsiz[2] != 4 || vsiz[3] != 5)
+    abort ();
+
+  vssz = vec_xxpermdi (vssx, vssy, 0b00);
+  vssz = vec_xxpermdi (vssx, vssy, vssy); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vusz = vec_xxpermdi (vusx, vusy, 0b00);
+  vusz = vec_xxpermdi (vusx, vusy, vusy); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  if (vssz[0] != 0 || vssz[1] != 1 || vssz[2] != 2 || vssz[3] != 3
+      || vssz[4] != 8 || vssz[5] != 9 || vssz[6] != 10 || vssz[7] != 11)
+    abort ();
+
+  vscz = vec_xxpermdi (vscx, vscy, 0b11);
+  vscz = vec_xxpermdi (vscx, vscy, vscy);/* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  vucz = vec_xxpermdi (vucx, vucy, 0b11);
+  vucz = vec_xxpermdi (vucx, vucy, vucy);/* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  if (vscz[0] != 8 || vscz[1] != 9 || vscz[2] != 10 || vscz[3] != 11
+      || vscz[4] != 12 || vscz[5] != 13 || vscz[6] != 14 || vscz[7] != 15
+      || vscz[8] != 24 || vscz[9] != 25 || vscz[10] != 26 || vscz[11] != 27
+      || vscz[12] != 28 || vscz[13] != 29 || vscz[14] != 30 || vscz[15] != 31)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr84220-xxsld.c b/gcc/testsuite/gcc.target/powerpc/pr84220-xxsld.c
new file mode 100644
index 0000000..06e485d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr84220-xxsld.c
@@ -0,0 +1,151 @@ 
+/* PR target/84220 */
+/* Test to ensure we generate invalid parameter errors rather than an ICE
+    when calling vec_xxsldwi() and vec_xxpermdi() with invalid parameters.  */
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+/* { dg-options "-O3 -mcpu=power7" } */
+
+#include <altivec.h>
+
+vector double
+v2df_shift (vector double a, vector double b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector float
+v4sf_shift (vector float a, vector float b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector long long
+v2di_shift (vector long long a, vector long long b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector unsigned long long
+v2diu_shift (vector unsigned long long a, vector unsigned long long b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector int
+v4si_shift (vector int a, vector int b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector unsigned int
+v4siu_shift (vector unsigned int a, vector unsigned int b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector short
+v8hi_shift (vector short a, vector short b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector unsigned short
+v8hiu_shift (vector unsigned short a, vector unsigned short b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector signed char
+v16qi_shift (vector signed char a, vector signed char b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector unsigned char
+v16qiu_shift (vector unsigned char a, vector unsigned char b)
+{
+  return vec_xxsldwi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxsldwi (a, b, 1);
+}
+
+vector double
+v2df_permute (vector double a, vector double b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector float
+v4sf_permute (vector float a, vector float b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector long long
+v2di_permute (vector long long a, vector long long b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector unsigned long long
+v2diu_permute (vector unsigned long long a, vector unsigned long long b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector int
+v4si_permute (vector int a, vector int b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector unsigned int
+v4siu_permute (vector unsigned int a, vector unsigned int b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector short
+v8hi_permute (vector short a, vector short b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+;
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector unsigned short
+v8hiu_permute (vector unsigned short a, vector unsigned short b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector signed char
+v16qi_permute (vector signed char a, vector signed char b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}
+
+vector unsigned char
+v16qiu_permute (vector unsigned char a, vector unsigned char b)
+{
+  return vec_xxpermdi (a, b, b); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */
+  return vec_xxpermdi (a, b, 1);
+}