From patchwork Tue Feb 13 17:34:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugeniy Paltsev X-Patchwork-Id: 873060 X-Patchwork-Delegate: alexey.brodkin@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zgqdl65v4z9sNr for ; Wed, 14 Feb 2018 04:43:39 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8754CC21FAE; Tue, 13 Feb 2018 17:38:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 81580C21F91; Tue, 13 Feb 2018 17:36:04 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BDE1FC21F9C; Tue, 13 Feb 2018 17:35:20 +0000 (UTC) Received: from smtprelay.synopsys.com (smtprelay4.synopsys.com [198.182.47.9]) by lists.denx.de (Postfix) with ESMTPS id 1CBD2C21F9E for ; Tue, 13 Feb 2018 17:35:17 +0000 (UTC) Received: from mailhost.synopsys.com (mailhost2.synopsys.com [10.13.184.66]) by smtprelay.synopsys.com (Postfix) with ESMTP id C112E24E0375 for ; Tue, 13 Feb 2018 09:35:15 -0800 (PST) Received: from localhost.internal.synopsys.com (unknown [10.121.3.43]) by mailhost.synopsys.com (Postfix) with ESMTP id 945802DB; Tue, 13 Feb 2018 09:35:14 -0800 (PST) From: Eugeniy Paltsev To: uboot-snps-arc@synopsys.com Date: Tue, 13 Feb 2018 20:34:46 +0300 Message-Id: <20180213173451.6317-14-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20180213173451.6317-1-Eugeniy.Paltsev@synopsys.com> References: <20180213173451.6317-1-Eugeniy.Paltsev@synopsys.com> Cc: u-boot@lists.denx.de, Alexey Brodkin , Eugeniy Paltsev Subject: [U-Boot] [PATCH 13/18] ARC: move IOC enabling to compile time options X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use CONFIG_ARC_DBG_IOC_ENABLE Kconfig option instead of ioc_enable global variable. Signed-off-by: Eugeniy Paltsev --- arch/arc/Kconfig | 18 ++++++++++++++++ arch/arc/include/asm/cache.h | 5 +++++ arch/arc/lib/cache.c | 49 ++++++++++++++++++++++++++------------------ 3 files changed, 52 insertions(+), 20 deletions(-) diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index e3f9db7..cc96fa8 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -116,6 +116,24 @@ config SYS_DCACHE_OFF bool "Do not use Data Cache" default n +menuconfig ARC_DBG + bool "ARC debugging" + default y + +if ARC_DBG + +config ARC_DBG_IOC_ENABLE + bool "Enable IO coherency unit" + depends on CPU_ARCHS38 + default n + help + Enable IO coherency unit to debug problems with caches and + DMA peripherals. + NOTE: as of today linux will not work properly if this option + is enabled in u-boot! + +endif + choice prompt "Target select" default TARGET_AXS103 diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 382c412..fe75409 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -32,6 +32,11 @@ void cache_init(void); void flush_n_invalidate_dcache_all(void); +static const inline int is_ioc_enabled(void) +{ + return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE); +} + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARC_CACHE_H */ diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index d31606c..df269cf 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -33,18 +33,8 @@ DECLARE_GLOBAL_DATA_PTR; #define SLC_CTRL_BUSY 0x100 #define SLC_CTRL_RGN_OP_INV 0x200 -/* - * By default that variable will fall into .bss section. - * But .bss section is not relocated and so it will be initilized before - * relocation but will be used after being zeroed. - */ #define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1)) -bool ioc_exists __section(".data") = false; - -/* To force enable IOC set ioc_enable to 'true' */ -bool ioc_enable __section(".data") = false; - static inline bool pae_exists(void) { /* TODO: should we compare mmu version from BCR and from CONFIG? */ @@ -88,6 +78,30 @@ static inline bool slc_exists(void) return false; } +static inline bool ioc_exists(void) +{ + if (is_isa_arcv2()) { + union bcr_clust_cfg cbcr; + + cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); + return cbcr.fields.c; + } + + return false; +} + +static inline bool ioc_status(void) +{ + /* + * We check only CONFIG option instead of IOC HW state check as IOC + * must be disabled by default. + */ + if (is_ioc_enabled()) + return ioc_exists(); + + return false; +} + static inline bool slc_status(void) { /* TODO: HS 3.0 supports SLC disable so we need to check it here */ @@ -213,16 +227,11 @@ static void arc_ioc_setup(void) static void read_decode_cache_bcr_arcv2(void) { union bcr_slc_cfg slc_cfg; - union bcr_clust_cfg cbcr; if (slc_exists()) { slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; } - - cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); - if (cbcr.fields.c && ioc_enable) - ioc_exists = true; } void read_decode_cache_bcr(void) @@ -255,7 +264,7 @@ void cache_init(void) if (is_isa_arcv2()) read_decode_cache_bcr_arcv2(); - if (is_isa_arcv2() && ioc_exists) + if (is_isa_arcv2() && ioc_status()) arc_ioc_setup(); /* @@ -432,10 +441,10 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op * ARCv2 && IOC enabled -> nothing */ - if (!is_isa_arcv2() || !ioc_exists) + if (!is_isa_arcv2() || !ioc_status()) __dc_line_op(start, end - start, OP_INV); - if (is_isa_arcv2() && !ioc_exists) + if (is_isa_arcv2() && !ioc_status()) __slc_rgn_op(start, end - start, OP_INV); } @@ -449,10 +458,10 @@ void flush_dcache_range(unsigned long start, unsigned long end) * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op * ARCv2 && IOC enabled -> nothing */ - if (!is_isa_arcv2() || !ioc_exists) + if (!is_isa_arcv2() || !ioc_status()) __dc_line_op(start, end - start, OP_FLUSH); - if (is_isa_arcv2() && !ioc_exists) + if (is_isa_arcv2() && !ioc_status()) __slc_rgn_op(start, end - start, OP_FLUSH); }