[U-Boot,13/18] ARC: move IOC enabling to compile time options

Message ID 20180213173451.6317-14-Eugeniy.Paltsev@synopsys.com
State New
Delegated to: Alexey Brodkin
Headers show
Series
  • ARC: cache subsystem improvement/refactoring
Related show

Commit Message

Eugeniy Paltsev Feb. 13, 2018, 5:34 p.m.
Use CONFIG_ARC_DBG_IOC_ENABLE Kconfig option instead of
ioc_enable global variable.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
---
 arch/arc/Kconfig             | 18 ++++++++++++++++
 arch/arc/include/asm/cache.h |  5 +++++
 arch/arc/lib/cache.c         | 49 ++++++++++++++++++++++++++------------------
 3 files changed, 52 insertions(+), 20 deletions(-)

Patch

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index e3f9db7..cc96fa8 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -116,6 +116,24 @@  config SYS_DCACHE_OFF
 	bool "Do not use Data Cache"
 	default n
 
+menuconfig ARC_DBG
+	bool "ARC debugging"
+	default y
+
+if ARC_DBG
+
+config ARC_DBG_IOC_ENABLE
+	bool "Enable IO coherency unit"
+	depends on CPU_ARCHS38
+	default n
+	help
+	  Enable IO coherency unit to debug problems with caches and
+	  DMA peripherals.
+	  NOTE: as of today linux will not work properly if this option
+	  is enabled in u-boot!
+
+endif
+
 choice
 	prompt "Target select"
 	default TARGET_AXS103
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index 382c412..fe75409 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -32,6 +32,11 @@ 
 void cache_init(void);
 void flush_n_invalidate_dcache_all(void);
 
+static const inline int is_ioc_enabled(void)
+{
+	return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE);
+}
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __ASM_ARC_CACHE_H */
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index d31606c..df269cf 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -33,18 +33,8 @@  DECLARE_GLOBAL_DATA_PTR;
 #define SLC_CTRL_BUSY		0x100
 #define SLC_CTRL_RGN_OP_INV	0x200
 
-/*
- * By default that variable will fall into .bss section.
- * But .bss section is not relocated and so it will be initilized before
- * relocation but will be used after being zeroed.
- */
 #define CACHE_LINE_MASK		(~(gd->arch.l1_line_sz - 1))
 
-bool ioc_exists __section(".data") = false;
-
-/* To force enable IOC set ioc_enable to 'true' */
-bool ioc_enable __section(".data") = false;
-
 static inline bool pae_exists(void)
 {
 	/* TODO: should we compare mmu version from BCR and from CONFIG? */
@@ -88,6 +78,30 @@  static inline bool slc_exists(void)
 	return false;
 }
 
+static inline bool ioc_exists(void)
+{
+	if (is_isa_arcv2()) {
+		union bcr_clust_cfg cbcr;
+
+		cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
+		return cbcr.fields.c;
+	}
+
+	return false;
+}
+
+static inline bool ioc_status(void)
+{
+	/*
+	 * We check only CONFIG option instead of IOC HW state check as IOC
+	 * must be disabled by default.
+	 */
+	if (is_ioc_enabled())
+		return ioc_exists();
+
+	return false;
+}
+
 static inline bool slc_status(void)
 {
 	/* TODO: HS 3.0 supports SLC disable so we need to check it here */
@@ -213,16 +227,11 @@  static void arc_ioc_setup(void)
 static void read_decode_cache_bcr_arcv2(void)
 {
 	union bcr_slc_cfg slc_cfg;
-	union bcr_clust_cfg cbcr;
 
 	if (slc_exists()) {
 		slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
 		gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
 	}
-
-	cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
-	if (cbcr.fields.c && ioc_enable)
-		ioc_exists = true;
 }
 
 void read_decode_cache_bcr(void)
@@ -255,7 +264,7 @@  void cache_init(void)
 	if (is_isa_arcv2())
 		read_decode_cache_bcr_arcv2();
 
-	if (is_isa_arcv2() && ioc_exists)
+	if (is_isa_arcv2() && ioc_status())
 		arc_ioc_setup();
 
 	/*
@@ -432,10 +441,10 @@  void invalidate_dcache_range(unsigned long start, unsigned long end)
 	 * ARCv2 && no IOC        -> call __dc_line_op; call __slc_rgn_op
 	 * ARCv2 && IOC enabled   -> nothing
 	 */
-	if (!is_isa_arcv2() || !ioc_exists)
+	if (!is_isa_arcv2() || !ioc_status())
 		__dc_line_op(start, end - start, OP_INV);
 
-	if (is_isa_arcv2() && !ioc_exists)
+	if (is_isa_arcv2() && !ioc_status())
 		__slc_rgn_op(start, end - start, OP_INV);
 }
 
@@ -449,10 +458,10 @@  void flush_dcache_range(unsigned long start, unsigned long end)
 	 * ARCv2 && no IOC        -> call __dc_line_op; call __slc_rgn_op
 	 * ARCv2 && IOC enabled   -> nothing
 	 */
-	if (!is_isa_arcv2() || !ioc_exists)
+	if (!is_isa_arcv2() || !ioc_status())
 		__dc_line_op(start, end - start, OP_FLUSH);
 
-	if (is_isa_arcv2() && !ioc_exists)
+	if (is_isa_arcv2() && !ioc_status())
 		__slc_rgn_op(start, end - start, OP_FLUSH);
 }