From patchwork Tue Feb 13 17:34:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugeniy Paltsev X-Patchwork-Id: 873056 X-Patchwork-Delegate: alexey.brodkin@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zgqcw6Gw3z9sNr for ; Wed, 14 Feb 2018 04:42:56 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8CDABC21FA8; Tue, 13 Feb 2018 17:38:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 37478C21FCE; Tue, 13 Feb 2018 17:36:02 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2354CC21FD9; Tue, 13 Feb 2018 17:35:09 +0000 (UTC) Received: from smtprelay.synopsys.com (smtprelay2.synopsys.com [198.182.60.111]) by lists.denx.de (Postfix) with ESMTPS id 5B367C21F84 for ; Tue, 13 Feb 2018 17:35:06 +0000 (UTC) Received: from mailhost.synopsys.com (mailhost2.synopsys.com [10.13.184.66]) by smtprelay.synopsys.com (Postfix) with ESMTP id 0D57210C02C5 for ; Tue, 13 Feb 2018 09:35:05 -0800 (PST) Received: from localhost.internal.synopsys.com (unknown [10.121.3.43]) by mailhost.synopsys.com (Postfix) with ESMTP id BC5E31F3; Tue, 13 Feb 2018 09:35:03 -0800 (PST) From: Eugeniy Paltsev To: uboot-snps-arc@synopsys.com Date: Tue, 13 Feb 2018 20:34:39 +0300 Message-Id: <20180213173451.6317-7-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20180213173451.6317-1-Eugeniy.Paltsev@synopsys.com> References: <20180213173451.6317-1-Eugeniy.Paltsev@synopsys.com> Cc: u-boot@lists.denx.de, Alexey Brodkin , Eugeniy Paltsev Subject: [U-Boot] [PATCH 06/18] ARC: cache: move IOC initialization to separate function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Move IOC initialization to separate function from cache_init function. This is the preparation for the next patch when we will switch to is_isa_arcv2() function using instead of "CONFIG_ISA_ARCV2" ifdef using. Also it makes cache_init function clear. Signed-off-by: Eugeniy Paltsev --- arch/arc/lib/cache.c | 56 ++++++++++++++++++++++++++++------------------------ 1 file changed, 30 insertions(+), 26 deletions(-) diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index a22ffe5..5070e9f 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -157,6 +157,34 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); } + +static void arc_ioc_setup(void) +{ + /* IOC Aperture start is equal to DDR start */ + unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; + /* IOC Aperture size is equal to DDR size */ + long ap_size = CONFIG_SYS_SDRAM_SIZE; + + flush_n_invalidate_dcache_all(); + + if (!is_power_of_2(ap_size) || ap_size < 4096) + panic("IOC Aperture size must be power of 2 and bigger 4Kib"); + + /* + * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, + * so setting 0x11 implies 512M, 0x12 implies 1G... + */ + write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, + order_base_2(ap_size / 1024) - 2); + + /* IOC Aperture start must be aligned to the size of the aperture */ + if (ap_base % ap_size != 0) + panic("IOC Aperture start must be aligned to the size of the aperture"); + + write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); + write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); + write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); +} #endif /* CONFIG_ISA_ARCV2 */ #ifdef CONFIG_ISA_ARCV2 @@ -250,32 +278,8 @@ void cache_init(void) #ifdef CONFIG_ISA_ARCV2 read_decode_cache_bcr_arcv2(); - if (ioc_exists) { - /* IOC Aperture start is equal to DDR start */ - unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; - /* IOC Aperture size is equal to DDR size */ - long ap_size = CONFIG_SYS_SDRAM_SIZE; - - flush_n_invalidate_dcache_all(); - - if (!is_power_of_2(ap_size) || ap_size < 4096) - panic("IOC Aperture size must be power of 2 and bigger 4Kib"); - - /* - * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, - * so setting 0x11 implies 512M, 0x12 implies 1G... - */ - write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, - order_base_2(ap_size / 1024) - 2); - - /* IOC Aperture start must be aligned to the size of the aperture */ - if (ap_base % ap_size != 0) - panic("IOC Aperture start must be aligned to the size of the aperture"); - - write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); - write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); - write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); - } + if (ioc_exists) + arc_ioc_setup(); read_decode_mmu_bcr();