From patchwork Tue Feb 13 17:34:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugeniy Paltsev X-Patchwork-Id: 873052 X-Patchwork-Delegate: alexey.brodkin@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zgqbk4Wtbz9sNr for ; Wed, 14 Feb 2018 04:41:53 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 4F9E1C21FD2; Tue, 13 Feb 2018 17:40:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 17309C21F95; Tue, 13 Feb 2018 17:39:38 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D9FADC21FB9; Tue, 13 Feb 2018 17:35:29 +0000 (UTC) Received: from smtprelay.synopsys.com (us01smtprelay-2.synopsys.com [198.182.47.9]) by lists.denx.de (Postfix) with ESMTPS id 8905BC21FD0 for ; Tue, 13 Feb 2018 17:35:25 +0000 (UTC) Received: from mailhost.synopsys.com (mailhost2.synopsys.com [10.13.184.66]) by smtprelay.synopsys.com (Postfix) with ESMTP id 4267D24E00DD for ; Tue, 13 Feb 2018 09:35:24 -0800 (PST) Received: from localhost.internal.synopsys.com (unknown [10.121.3.43]) by mailhost.synopsys.com (Postfix) with ESMTP id 1901C370; Tue, 13 Feb 2018 09:35:22 -0800 (PST) From: Eugeniy Paltsev To: uboot-snps-arc@synopsys.com Date: Tue, 13 Feb 2018 20:34:51 +0300 Message-Id: <20180213173451.6317-19-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20180213173451.6317-1-Eugeniy.Paltsev@synopsys.com> References: <20180213173451.6317-1-Eugeniy.Paltsev@synopsys.com> Cc: u-boot@lists.denx.de, Alexey Brodkin , Eugeniy Paltsev Subject: [U-Boot] [PATCH 18/18] ARC: cache: add missing cache cleanup before cache disable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add missing cache cleanup before cache disable: * Flush and invalidate L1 D$ before disabling. Otherwise we can lose some data when we disable L1 D$ if this data isn't flushed to next level cache. Or we can get wrong data if L1 D$ has some entries after enable which we modified when the L1 D$ was disabled. * Invalidate L1 I$ before disabling. Otherwise we can execute wrong instructions after L1 I$ enable if we modified any code when L1 I$ was disabled. Signed-off-by: Eugeniy Paltsev --- arch/arc/lib/cache.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 907e9e3..ba442fb 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -15,6 +15,9 @@ DECLARE_GLOBAL_DATA_PTR; +static inline void __ic_entire_invalidate(void); +static inline void __dc_entire_op(const int cacheop); + /* Bit values in IC_CTRL */ #define IC_CTRL_CACHE_DISABLE BIT(0) @@ -299,9 +302,13 @@ void icache_enable(void) void icache_disable(void) { - if (icache_exists()) - write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | - IC_CTRL_CACHE_DISABLE); + if (!icache_exists()) + return; + + __ic_entire_invalidate(); + + write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | + IC_CTRL_CACHE_DISABLE); } /* IC supports only invalidation */ @@ -358,6 +365,8 @@ void dcache_disable(void) if (!dcache_exists()) return; + __dc_entire_op(OP_FLUSH_N_INV); + write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | DC_CTRL_CACHE_DISABLE); }