From patchwork Tue Feb 13 15:28:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yannick FERTRE X-Patchwork-Id: 872920 X-Patchwork-Delegate: agust@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zgmkp5qxhz9t3F for ; Wed, 14 Feb 2018 02:32:50 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 638D4C21F07; Tue, 13 Feb 2018 15:30:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3A261C21F8C; Tue, 13 Feb 2018 15:30:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 12966C21F07; Tue, 13 Feb 2018 15:28:45 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id B4252C21DD7 for ; Tue, 13 Feb 2018 15:28:45 +0000 (UTC) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w1DFJSG1016245; Tue, 13 Feb 2018 16:28:45 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2g22rywefd-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 13 Feb 2018 16:28:45 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9690034; Tue, 13 Feb 2018 15:28:44 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 870984F0B; Tue, 13 Feb 2018 15:28:44 +0000 (GMT) Received: from SAFEX1HUBCAS22.st.com (10.75.90.92) by SAFEX1HUBCAS23.st.com (10.75.90.46) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 13 Feb 2018 16:28:44 +0100 Received: from localhost (10.201.23.68) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.352.0; Tue, 13 Feb 2018 16:28:44 +0100 From: yannick fertre To: Yannick Fertre , Benjamin Gaignard , Philippe CORNU , "Patrice CHOTARD" , Anatolij Gustschin Date: Tue, 13 Feb 2018 16:28:29 +0100 Message-ID: <1518535713-787-4-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518535713-787-1-git-send-email-yannick.fertre@st.com> References: <1518535713-787-1-git-send-email-yannick.fertre@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.68] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-13_08:, , signatures=0 X-Mailman-Approved-At: Tue, 13 Feb 2018 15:30:00 +0000 Cc: Andrzej Hajda , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v1 3/7] video: stm32: stm32_ltdc: set rate of the pixel clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" pxclk is useless to set pixel clock. Signed-off-by: yannick fertre --- drivers/video/stm32/stm32_ltdc.c | 52 ++++++++++++++++++++++------------------ 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index 8d89b58..08e0afc 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -301,9 +301,9 @@ static int stm32_ltdc_probe(struct udevice *dev) struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct stm32_ltdc_priv *priv = dev_get_priv(dev); struct udevice *panel; - struct clk pclk, pxclk; + struct clk pclk; struct reset_ctl rst; - int ret; + int rate, ret; priv->regs = (void *)dev_read_addr(dev); if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) { @@ -311,9 +311,16 @@ static int stm32_ltdc_probe(struct udevice *dev) return -EINVAL; } - ret = uclass_first_device(UCLASS_PANEL, &panel); + ret = clk_get_by_index(dev, 0, &pclk); if (ret) { - debug("%s: panel device error %d\n", __func__, ret); + debug("%s: peripheral clock get error %d\n", __func__, ret); + return ret; + } + + ret = clk_enable(&pclk); + if (ret) { + debug("%s: peripheral clock enable error %d\n", + __func__, ret); return ret; } @@ -326,6 +333,12 @@ static int stm32_ltdc_probe(struct udevice *dev) /* Reset */ reset_deassert(&rst); + ret = uclass_first_device(UCLASS_PANEL, &panel); + if (ret) { + debug("%s: panel device error %d\n", __func__, ret); + return ret; + } + ret = panel_enable_backlight(panel); if (ret) { debug("%s: panel %s enable backlight error %d\n", @@ -333,31 +346,24 @@ static int stm32_ltdc_probe(struct udevice *dev) return ret; } - ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev), - 0, &priv->timing); + ret = fdtdec_decode_display_timing(gd->fdt_blob, + dev_of_offset(dev), 0, + &priv->timing); if (ret) { - debug("%s: decode display timing error %d\n", __func__, ret); + debug("%s: decode display timing error %d\n", + __func__, ret); return -EINVAL; } - ret = clk_get_by_name(dev, "pclk", &pclk); - if (ret) { - debug("%s: peripheral clock get error %d\n", __func__, ret); - return ret; + rate = clk_set_rate(&pclk, priv->timing.pixelclock.typ); + if (rate < 0) { + debug("%s: fail to set pixel clock %d hz %d hz\n", + __func__, priv->timing.pixelclock.typ, rate); + return rate; } - ret = clk_enable(&pclk); - if (ret) { - debug("%s: peripheral clock enable error %d\n", __func__, ret); - return ret; - } - - /* Verify pixel clock value if any & inform user accordingly */ - ret = clk_get_by_name(dev, "pxclk", &pxclk); - if (!ret) { - if (clk_get_rate(&pxclk) != priv->timing.pixelclock.typ) - printf("Warning: please adjust ltdc pixel clock\n"); - } + debug("%s: Set pixel clock req %d hz get %d hz\n", __func__, + priv->timing.pixelclock.typ, rate); /* TODO Below parameters are hard-coded for the moment... */ priv->l2bpp = VIDEO_BPP16;