From patchwork Mon Feb 12 17:26:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Preetham Chandru Ramchandra X-Patchwork-Id: 872199 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zgCKp2dDyz9sBZ for ; Tue, 13 Feb 2018 04:27:42 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753291AbeBLR1l (ORCPT ); Mon, 12 Feb 2018 12:27:41 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5070 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753033AbeBLR1k (ORCPT ); Mon, 12 Feb 2018 12:27:40 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 12 Feb 2018 09:27:44 -0800 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 12 Feb 2018 09:27:40 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 12 Feb 2018 09:27:40 -0800 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 12 Feb 2018 17:27:40 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 12 Feb 2018 17:27:40 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Mon, 12 Feb 2018 17:27:40 +0000 Received: from pchandru-pc.nvidia.com (Not Verified[10.24.37.8]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 12 Feb 2018 09:27:39 -0800 From: Preetham Chandru Ramchandra To: , , , , , CC: , , , , , Preetham Ramchandra Subject: [PATCH V7 4/7] ata: ahci_tegra: initialize regulators from soc_data Date: Mon, 12 Feb 2018 22:56:43 +0530 Message-ID: <1518456406-21564-5-git-send-email-pchandru@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518456406-21564-1-git-send-email-pchandru@nvidia.com> References: <1518456406-21564-1-git-send-email-pchandru@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Preetham Ramchandra Get the regulator names to be initialized from soc_data and initialize them. Signed-off-by: Preetham Chandru R Acked-by: Thierry Reding --- v7: * moved tegra124_supply_names definition to just above the tegra124_ahci_soc_data structure. --- drivers/ata/ahci_tegra.c | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c index 7ffe8a97447a..6aaf8a4571c8 100644 --- a/drivers/ata/ahci_tegra.c +++ b/drivers/ata/ahci_tegra.c @@ -164,6 +164,8 @@ struct tegra_ahci_ops { }; struct tegra_ahci_soc { + const char *const *supply_names; + u32 num_supplies; struct tegra_ahci_ops ops; }; @@ -175,7 +177,7 @@ struct tegra_ahci_priv { struct reset_control *sata_cold_rst; /* Needs special handling, cannot use ahci_platform */ struct clk *sata_clk; - struct regulator_bulk_data supplies[5]; + struct regulator_bulk_data *supplies; struct tegra_ahci_soc *soc_data; }; @@ -228,7 +230,7 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv) struct tegra_ahci_priv *tegra = hpriv->plat_data; int ret; - ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies), + ret = regulator_bulk_enable(tegra->soc_data->num_supplies, tegra->supplies); if (ret) return ret; @@ -257,7 +259,7 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv) tegra_powergate_power_off(TEGRA_POWERGATE_SATA); disable_regulators: - regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies); + regulator_bulk_disable(tegra->soc_data->num_supplies, tegra->supplies); return ret; } @@ -274,7 +276,7 @@ static void tegra_ahci_power_off(struct ahci_host_priv *hpriv) clk_disable_unprepare(tegra->sata_clk); tegra_powergate_power_off(TEGRA_POWERGATE_SATA); - regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies); + regulator_bulk_disable(tegra->soc_data->num_supplies, tegra->supplies); } static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv) @@ -432,7 +434,13 @@ static const struct ata_port_info ahci_tegra_port_info = { .port_ops = &ahci_tegra_port_ops, }; +static const char *const tegra124_supply_names[] = { + "avdd", "hvdd", "vddio", "target-5v", "target-12v" +}; + static const struct tegra_ahci_soc tegra124_ahci_soc_data = { + .supply_names = tegra124_supply_names, + .num_supplies = ARRAY_SIZE(tegra124_supply_names), .ops = { .init = tegra124_ahci_init, }, @@ -457,6 +465,7 @@ static int tegra_ahci_probe(struct platform_device *pdev) struct tegra_ahci_priv *tegra; struct resource *res; int ret; + unsigned int i; hpriv = ahci_platform_get_resources(pdev); if (IS_ERR(hpriv)) @@ -501,13 +510,17 @@ static int tegra_ahci_probe(struct platform_device *pdev) return PTR_ERR(tegra->sata_clk); } - tegra->supplies[0].supply = "avdd"; - tegra->supplies[1].supply = "hvdd"; - tegra->supplies[2].supply = "vddio"; - tegra->supplies[3].supply = "target-5v"; - tegra->supplies[4].supply = "target-12v"; + tegra->supplies = devm_kcalloc(&pdev->dev, + tegra->soc_data->num_supplies, + sizeof(*tegra->supplies), GFP_KERNEL); + if (!tegra->supplies) + return -ENOMEM; + + for (i = 0; i < tegra->soc_data->num_supplies; i++) + tegra->supplies[i].supply = tegra->soc_data->supply_names[i]; - ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra->supplies), + ret = devm_regulator_bulk_get(&pdev->dev, + tegra->soc_data->num_supplies, tegra->supplies); if (ret) { dev_err(&pdev->dev, "Failed to get regulators\n");