From patchwork Fri Feb 9 21:40:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sukadev Bhattiprolu X-Patchwork-Id: 871572 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zdT4v4wx8z9s72 for ; Sat, 10 Feb 2018 08:40:31 +1100 (AEDT) Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zdT4v0Sl7zF0b8 for ; Sat, 10 Feb 2018 08:40:31 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=sukadev@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zdT4m1KtbzDrDK for ; Sat, 10 Feb 2018 08:40:23 +1100 (AEDT) Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w19Lct6Q034614 for ; Fri, 9 Feb 2018 16:40:21 -0500 Received: from e12.ny.us.ibm.com (e12.ny.us.ibm.com [129.33.205.202]) by mx0b-001b2d01.pphosted.com with ESMTP id 2g1kfcrhxn-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 09 Feb 2018 16:40:21 -0500 Received: from localhost by e12.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 9 Feb 2018 16:40:20 -0500 Received: from b01cxnp23034.gho.pok.ibm.com (9.57.198.29) by e12.ny.us.ibm.com (146.89.104.199) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Fri, 9 Feb 2018 16:40:18 -0500 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp23034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w19LeHXe45613128; Fri, 9 Feb 2018 21:40:17 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 907E812403D; Fri, 9 Feb 2018 16:37:03 -0500 (EST) Received: from suka-w540.localdomain (unknown [9.70.94.25]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP id 3D211124035; Fri, 9 Feb 2018 16:37:03 -0500 (EST) Received: by suka-w540.localdomain (Postfix, from userid 1000) id EABF52292A2; Fri, 9 Feb 2018 13:40:15 -0800 (PST) Date: Fri, 9 Feb 2018 13:40:15 -0800 From: Sukadev Bhattiprolu To: stewart@linux.vnet.ibm.com MIME-Version: 1.0 Content-Disposition: inline X-Operating-System: Linux 2.0.32 on an i486 User-Agent: Mutt/1.7.1 (2016-10-04) X-TM-AS-GCONF: 00 x-cbid: 18020921-0048-0000-0000-0000023511E1 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008506; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000251; SDB=6.00987374; UDB=6.00501171; IPR=6.00766732; BA=6.00005821; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00019468; XFM=3.00000015; UTC=2018-02-09 21:40:19 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18020921-0049-0000-0000-000044132631 Message-Id: <20180209214015.GA12579@us.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-09_11:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1802090274 Subject: [Skiboot] [PATCH] vas: Disable VAS/NX-842 on some P9 revisions X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mikey@neuling.org, skiboot@lists.ozlabs.org, hbabu@us.ibm.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" VAS/NX-842 are not functional on some P9 revisions, so disable them in hardware and skip creating their device tree nodes. Since the intent is to prevent OS from configuring VAS/NX, we remove only the platform device nodes but leave the VAS/NX DT nodes under xscom (i.e we don't skip add_vas_node() in hdata/spira.c) Thanks to input from Michael Ellerman, Michael Neuling. Signed-off-by: Sukadev Bhattiprolu Signed-off-by: Sukadev Bhattiprolu Reviewed-by: Michael Ellerman --- hw/nx.c | 5 +++++ hw/vas.c | 47 ++++++++++++++++++++++++++++++++++++++++++++--- include/vas.h | 1 + 3 files changed, 50 insertions(+), 3 deletions(-) diff --git a/hw/nx.c b/hw/nx.c index 0f6ff04..784a553 100644 --- a/hw/nx.c +++ b/hw/nx.c @@ -24,6 +24,7 @@ #include #include #include +#include #include static void p9_darn_init(void) @@ -110,6 +111,10 @@ void nx_p9_rng_late_init(void) static void nx_init_one(struct dt_node *node) { nx_create_rng_node(node); + + if (vas_nx_disabled()) + return; + nx_create_crypto_node(node); nx_create_compress_node(node); } diff --git a/hw/vas.c b/hw/vas.c index fb5a1e7..6362f7e 100644 --- a/hw/vas.c +++ b/hw/vas.c @@ -69,6 +69,36 @@ static int vas_scom_write(struct proc_chip *chip, uint64_t reg, uint64_t val) return rc; } +/* + * VAS and hence, NX-842 are disabled in following POWER9 revisions: + * + * - Nimbus DD1.X, DD2.01, DD2.1 + * - Cumulus DD1.0 + * + * Return true for those revisions. Return false for others. + */ +__attrconst inline bool vas_nx_disabled(void) +{ + uint32_t pvr; + int major, minor; + struct proc_chip *chip; + + chip = next_chip(NULL); + + pvr = mfspr(SPR_PVR); + major = PVR_VERS_MAJ(pvr); + minor = PVR_VERS_MIN(pvr); + + switch (chip->type) { + case PROC_CHIP_P9_NIMBUS: + return (major < 2 || (major == 2 && minor <= 1)); + case PROC_CHIP_P9_CUMULUS: + return (major == 1 && minor == 0); + default: + return false; + } +} + /* Interface for NX - make sure VAS is fully initialized first */ __attrconst inline uint64_t vas_get_hvwc_mmio_bar(const int chipid) { @@ -110,6 +140,9 @@ static int init_north_ctl(struct proc_chip *chip) return vas_scom_write(chip, VAS_MISC_N_CTL, val); } +/* + * Ensure paste instructions are not accepted and MMIO BARs are disabled. + */ static inline int reset_north_ctl(struct proc_chip *chip) { return vas_scom_write(chip, VAS_MISC_N_CTL, 0ULL); @@ -399,7 +432,7 @@ static void disable_vas_inst(struct dt_node *np) /* * Initialize one VAS instance */ -static int init_vas_inst(struct dt_node *np) +static int init_vas_inst(struct dt_node *np, bool disabled) { uint32_t vas_id; uint64_t xscom_base; @@ -411,6 +444,11 @@ static int init_vas_inst(struct dt_node *np) chip->vas = alloc_vas(chip->id, vas_id, xscom_base); + if (disabled) { + reset_north_ctl(chip); + return 0; + } + if (alloc_init_wcbs(chip)) return -1; @@ -429,17 +467,20 @@ static int init_vas_inst(struct dt_node *np) void vas_init() { + bool disabled; struct dt_node *np; if (proc_gen != proc_gen_p9) return; + disabled = vas_nx_disabled(); + dt_for_each_compatible(dt_root, np, "ibm,power9-vas-x") { - if (init_vas_inst(np)) + if (init_vas_inst(np, disabled)) goto out; } - vas_initialized = 1; + vas_initialized = !disabled; return; out: diff --git a/include/vas.h b/include/vas.h index 6bc2a1c..2e37908 100644 --- a/include/vas.h +++ b/include/vas.h @@ -37,6 +37,7 @@ */ extern void vas_init(void); +extern __attrconst bool vas_nx_disabled(void); extern __attrconst uint64_t vas_get_hvwc_mmio_bar(const int chipid); extern __attrconst uint64_t vas_get_wcbs_bar(int chipid);