diff mbox series

[U-Boot,2/7] clk: clk_stm32f: Fix RCC_PLLSAICFGR mask defines

Message ID 1518106851-18106-3-git-send-email-patrice.chotard@st.com
State Accepted
Commit 526aa92960cfea5d6799b5a6aae89e4e646acc67
Delegated to: Tom Rini
Headers show
Series clk: clk_stm32f: update and fixes | expand

Commit Message

Patrice CHOTARD Feb. 8, 2018, 4:20 p.m. UTC 
From: Patrice Chotard <patrice.chotard@st.com>

Use the correct name for RCC_PLLSAICFGR_PLLSAIx_MASK masks.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
 drivers/clk/clk_stm32f.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Tom Rini March 14, 2018, 2:08 p.m. UTC | #1 
On Thu, Feb 08, 2018 at 05:20:46PM +0100, patrice.chotard@st.com wrote:

> From: Patrice Chotard <patrice.chotard@st.com>
> 
> Use the correct name for RCC_PLLSAICFGR_PLLSAIx_MASK masks.
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c
index 41d8b5e5c88a..7d89906379af 100644
--- a/drivers/clk/clk_stm32f.c
+++ b/drivers/clk/clk_stm32f.c
@@ -55,8 +55,8 @@ 
 #define RCC_CFGR_PPRE1_SHIFT		10
 #define RCC_CFGR_PPRE2_SHIFT		13
 
-#define RCC_PLLCFGR_PLLSAIN_MASK	GENMASK(14, 6)
-#define RCC_PLLCFGR_PLLSAIP_MASK	GENMASK(17, 16)
+#define RCC_PLLSAICFGR_PLLSAIN_MASK	GENMASK(14, 6)
+#define RCC_PLLSAICFGR_PLLSAIP_MASK	GENMASK(17, 16)
 #define RCC_PLLSAICFGR_PLLSAIN_SHIFT	6
 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT	16
 #define RCC_PLLSAICFGR_PLLSAIP_4	BIT(16)
@@ -247,9 +247,9 @@  static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv,
 	if (pllsai) {
 		/* PLL48CLK is selected from PLLSAI, get PLLSAI value */
 		pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
-		pllsain = ((readl(&regs->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK)
+		pllsain = ((readl(&regs->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK)
 			>> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
-		pllsaip = ((((readl(&regs->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK)
+		pllsaip = ((((readl(&regs->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIP_MASK)
 			>> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
 		return ((priv->hse_rate / pllm) * pllsain) / pllsaip;
 	}