From patchwork Wed Feb 7 06:50:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Donnellan X-Patchwork-Id: 870248 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zbsT12Y3pz9ryk for ; Wed, 7 Feb 2018 17:52:21 +1100 (AEDT) Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zbsT11SN7zF10c for ; Wed, 7 Feb 2018 17:52:21 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=au1.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=andrew.donnellan@au1.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zbsRl1HjkzF0Sb for ; Wed, 7 Feb 2018 17:51:14 +1100 (AEDT) Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w176oFvE002059 for ; Wed, 7 Feb 2018 01:51:13 -0500 Received: from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110]) by mx0a-001b2d01.pphosted.com with ESMTP id 2fyt87vx6f-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 07 Feb 2018 01:51:12 -0500 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 7 Feb 2018 06:51:08 -0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w176p8gm49152114; Wed, 7 Feb 2018 06:51:08 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 296B54C052; Wed, 7 Feb 2018 06:44:59 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 81D8C4C058; Wed, 7 Feb 2018 06:44:58 +0000 (GMT) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 7 Feb 2018 06:44:58 +0000 (GMT) Received: from intelligence.au.ibm.com (unknown [9.192.255.83]) (using TLSv1.2 with cipher DHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 43182A025B; Wed, 7 Feb 2018 17:51:06 +1100 (AEDT) From: Andrew Donnellan To: skiboot@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com Date: Wed, 7 Feb 2018 17:50:47 +1100 X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-TM-AS-GCONF: 00 x-cbid: 18020706-0016-0000-0000-00000520334C X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18020706-0017-0000-0000-0000285CE7C2 Message-Id: X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-07_01:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1802070086 Subject: [Skiboot] [PATCH v5 01/10] npu2: Split out common helper functions into separate file X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au, arbab@linux.vnet.ibm.com MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Split out common helper functions for NPU register access into a separate file, as these will be used extensively by both NVLink and OpenCAPI code. Signed-off-by: Andrew Donnellan Acked-by: Reza Arbab --- v1->v2: - Add copyright header (Fred) --- hw/Makefile.inc | 2 +- hw/npu2-common.c | 114 +++++++++++++++++++++++++++++++++++++++++++++- hw/npu2.c | 92 +------------------------------------ include/npu2-regs.h | 5 ++- include/npu2.h | 2 +- 5 files changed, 122 insertions(+), 93 deletions(-) create mode 100644 hw/npu2-common.c diff --git a/hw/Makefile.inc b/hw/Makefile.inc index 04cacd12c408..cf8649d00270 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -7,7 +7,7 @@ HW_OBJS += p7ioc.o p7ioc-inits.o p7ioc-phb.o HW_OBJS += phb3.o sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o -HW_OBJS += phys-map.o sbe-p9.o capp.o occ-sensor.o vas.o +HW_OBJS += npu2-common.o phys-map.o sbe-p9.o capp.o occ-sensor.o vas.o HW=hw/built-in.o # FIXME hack this for now diff --git a/hw/npu2-common.c b/hw/npu2-common.c new file mode 100644 index 000000000000..0c22d6188819 --- /dev/null +++ b/hw/npu2-common.c @@ -0,0 +1,114 @@ +/* Copyright 2013-2018 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#include +#include + +bool is_p9dd1(void) +{ + struct proc_chip *chip = next_chip(NULL); + + return chip && + (chip->type == PROC_CHIP_P9_NIMBUS || + chip->type == PROC_CHIP_P9_CUMULUS) && + (chip->ec_level & 0xf0) == 0x10; +} + +/* + * We use the indirect method because it uses the same addresses as + * the MMIO offsets (NPU RING) + */ +static void npu2_scom_set_addr(uint64_t gcid, uint64_t scom_base, + uint64_t addr, uint64_t size) +{ + uint64_t isa = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_ADDR : + NPU2_MISC_SCOM_IND_SCOM_ADDR; + + addr = SETFIELD(NPU2_MISC_DA_ADDR, 0ull, addr); + addr = SETFIELD(NPU2_MISC_DA_LEN, addr, size); + xscom_write(gcid, scom_base + isa, addr); +} + +void npu2_scom_write(uint64_t gcid, uint64_t scom_base, + uint64_t reg, uint64_t size, + uint64_t val) +{ + uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : + NPU2_MISC_SCOM_IND_SCOM_DATA; + + npu2_scom_set_addr(gcid, scom_base, reg, size); + xscom_write(gcid, scom_base + isd, val); +} + +uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base, + uint64_t reg, uint64_t size) +{ + uint64_t val; + uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : + NPU2_MISC_SCOM_IND_SCOM_DATA; + + npu2_scom_set_addr(gcid, scom_base, reg, size); + xscom_read(gcid, scom_base + isd, &val); + + return val; +} + +void npu2_write_4b(struct npu2 *p, uint64_t reg, uint32_t val) +{ + npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B, + (uint64_t)val << 32); +} + +uint32_t npu2_read_4b(struct npu2 *p, uint64_t reg) +{ + return npu2_scom_read(p->chip_id, p->xscom_base, reg, + NPU2_MISC_DA_LEN_4B) >> 32; +} + +void npu2_write(struct npu2 *p, uint64_t reg, uint64_t val) +{ + npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, val); +} + +uint64_t npu2_read(struct npu2 *p, uint64_t reg) +{ + return npu2_scom_read(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B); +} + +void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask) +{ + uint64_t new_val; + + new_val = npu2_read(p, reg); + new_val &= ~mask; + new_val |= val & mask; + npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, new_val); +} + +void npu2_write_mask_4b(struct npu2 *p, uint64_t reg, uint32_t val, uint32_t mask) +{ + uint32_t new_val; + + new_val = npu2_read_4b(p, reg); + new_val &= ~mask; + new_val |= val & mask; + npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B, + (uint64_t)new_val << 32); +} diff --git a/hw/npu2.c b/hw/npu2.c index c88394b678d6..41c30f404593 100644 --- a/hw/npu2.c +++ b/hw/npu2.c @@ -64,98 +64,6 @@ * configure one particular BAR. */ -static bool is_p9dd1(void) -{ - struct proc_chip *chip = next_chip(NULL); - - return chip && - (chip->type == PROC_CHIP_P9_NIMBUS || - chip->type == PROC_CHIP_P9_CUMULUS) && - (chip->ec_level & 0xf0) == 0x10; -} - -/* - * We use the indirect method because it uses the same addresses as - * the MMIO offsets (NPU RING) - */ -static void npu2_scom_set_addr(uint64_t gcid, uint64_t scom_base, - uint64_t addr, uint64_t size) -{ - uint64_t isa = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_ADDR : - NPU2_MISC_SCOM_IND_SCOM_ADDR; - - addr = SETFIELD(NPU2_MISC_DA_ADDR, 0ull, addr); - addr = SETFIELD(NPU2_MISC_DA_LEN, addr, size); - xscom_write(gcid, scom_base + isa, addr); -} - -static void npu2_scom_write(uint64_t gcid, uint64_t scom_base, - uint64_t reg, uint64_t size, - uint64_t val) -{ - uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : - NPU2_MISC_SCOM_IND_SCOM_DATA; - - npu2_scom_set_addr(gcid, scom_base, reg, size); - xscom_write(gcid, scom_base + isd, val); -} - -static uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base, - uint64_t reg, uint64_t size) -{ - uint64_t val; - uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : - NPU2_MISC_SCOM_IND_SCOM_DATA; - - npu2_scom_set_addr(gcid, scom_base, reg, size); - xscom_read(gcid, scom_base + isd, &val); - - return val; -} - -void npu2_write_4b(struct npu2 *p, uint64_t reg, uint32_t val) -{ - npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B, - (uint64_t)val << 32); -} - -uint32_t npu2_read_4b(struct npu2 *p, uint64_t reg) -{ - return npu2_scom_read(p->chip_id, p->xscom_base, reg, - NPU2_MISC_DA_LEN_4B) >> 32; -} - -void npu2_write(struct npu2 *p, uint64_t reg, uint64_t val) -{ - npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, val); -} - -uint64_t npu2_read(struct npu2 *p, uint64_t reg) -{ - return npu2_scom_read(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B); -} - -void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask) -{ - uint64_t new_val; - - new_val = npu2_read(p, reg); - new_val &= ~mask; - new_val |= val & mask; - npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, new_val); -} - -void npu2_write_mask_4b(struct npu2 *p, uint64_t reg, uint32_t val, uint32_t mask) -{ - uint32_t new_val; - - new_val = npu2_read_4b(p, reg); - new_val &= ~mask; - new_val |= val & mask; - npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B, - (uint64_t)new_val << 32); -} - /* Set a specific flag in the vendor config space */ void npu2_set_link_flag(struct npu2_dev *ndev, uint8_t flag) { diff --git a/include/npu2-regs.h b/include/npu2-regs.h index e739ac5091a6..b190d0f0767a 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -23,6 +23,11 @@ void npu2_write4(struct npu2 *p, uint64_t reg, uint64_t val); uint64_t npu2_read(struct npu2 *p, uint64_t reg); void npu2_write(struct npu2 *p, uint64_t reg, uint64_t val); void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); +uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base, + uint64_t reg, uint64_t size); +void npu2_scom_write(uint64_t gcid, uint64_t scom_base, + uint64_t reg, uint64_t size, + uint64_t val); /* These aren't really NPU specific registers but we initialise them in NPU * code */ diff --git a/include/npu2.h b/include/npu2.h index dae152a6b034..d0c9ac502a70 100644 --- a/include/npu2.h +++ b/include/npu2.h @@ -163,4 +163,6 @@ void npu2_dev_procedure_reset(struct npu2_dev *dev); void npu2_set_link_flag(struct npu2_dev *ndev, uint8_t flag); void npu2_clear_link_flag(struct npu2_dev *ndev, uint8_t flag); extern int nv_zcal_nominal; +bool is_p9dd1(void); + #endif /* __NPU2_H */