| Message ID | 1517934852-23255-12-git-send-email-pdeschrijver@nvidia.com |
|---|---|
| State | Deferred |
| Headers | show |
| Series | Tegra210 DFLL implementation | expand |
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index bc9851a..a7fddae 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1229,6 +1229,13 @@ device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0>; + clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, + <&tegra_car TEGRA210_CLK_PLL_X>, + <&tegra_car TEGRA210_CLK_PLL_P_OUT_CPU>, + <&dfll>; + clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; + /* FIXME: what's the actual transition time? */ + clock-latency = <300000>; }; cpu@1 {
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)