From patchwork Tue Feb 6 16:34:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 869887 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zbVSV2fgYz9sNx for ; Wed, 7 Feb 2018 03:35:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752761AbeBFQfb (ORCPT ); Tue, 6 Feb 2018 11:35:31 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:18959 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752612AbeBFQeo (ORCPT ); Tue, 6 Feb 2018 11:34:44 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 06 Feb 2018 08:34:48 -0800 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 06 Feb 2018 08:34:43 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 06 Feb 2018 08:34:43 -0800 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 6 Feb 2018 16:34:43 +0000 Received: from tbergstrom-lnx.Nvidia.com (10.21.24.170) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 6 Feb 2018 16:34:37 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id CBAC7F816A3; Tue, 6 Feb 2018 18:34:33 +0200 (EET) From: Peter De Schrijver To: , , , , , , , , , CC: Peter De Schrijver Subject: [PATCH v3 10/11] arm64: dts: tegra: Add Tegra210 DFLL definition Date: Tue, 6 Feb 2018 18:34:11 +0200 Message-ID: <1517934852-23255-11-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517934852-23255-1-git-send-email-pdeschrijver@nvidia.com> References: <1517934852-23255-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Signed-off-by: Peter De Schrijver --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 18 ++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 212e663..19720b5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -284,6 +284,24 @@ non-removable; }; + clock@70110000 { + status = "okay"; + nvidia,pwm-to-pmic; + nvidia,init-uv = <1000000>; + nvidia,align-step-uv = <19200>; /* 19.2mV */ + nvidia,align-offset-uv = <708000>; /* 708mV */ + nvidia,sample-rate = <25000>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <6>; + nvidia,ci = <0>; + nvidia,cg = <2>; + nvidia,pwm-period = <2500>; /* 2.5us */ + pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; + pinctrl-0 = <&dvfs_pwm_active_state>; + pinctrl-1 = <&dvfs_pwm_inactive_state>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index d67ef43..8145aef 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1278,6 +1278,18 @@ nvidia,open-drain = ; }; }; + dvfs_pwm_active_state: dvfs_pwm_active { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; + dvfs_pwm_inactive_state: dvfs_pwm_inactive { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; }; pwm@7000a000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 9c24021..bc9851a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include #include @@ -1056,6 +1057,24 @@ #nvidia,mipi-calibrate-cells = <1>; }; + dfll: clock@70110000 { + compatible = "nvidia,tegra210-dfll"; + reg = <0 0x70110000 0 0x100>, /* DFLL control */ + <0 0x70110000 0 0x100>, /* I2C output control */ + <0 0x70110100 0 0x100>, /* Integrated I2C controller */ + <0 0x70110200 0 0x100>; /* Look-up table RAM */ + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, + <&tegra_car TEGRA210_CLK_DFLL_REF>; + clock-names = "soc", "ref"; + resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + out-clock-name="dfll_cpu"; + status = "disabled"; + }; + aconnect@702c0000 { compatible = "nvidia,tegra210-aconnect"; clocks = <&tegra_car TEGRA210_CLK_APE>,