[U-Boot,1/6] Add Broadwell-DE architecture cpu files

diff --git a/arch/x86/cpu/broadwell-de/Kconfig b/arch/x86/cpu/broadwell-de/Kconfig
new file mode 100644
index 0000000000..4e7b72c81c
--- /dev/null
+++ b/arch/x86/cpu/broadwell-de/Kconfig
@@ -0,0 +1,66 @@ 
+#
+# Copyright (C) 2017, Vincenzo Bove <vincenzo.bove@prodrive-technologies.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+config INTEL_BROADWELL_DE
+ bool
+ select HAVE_FSP
+ select ARCH_MISC_INIT
+ select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+ imply HAVE_INTEL_ME
+ imply ENABLE_MRC_CACHE
+ imply AHCI_PCI
+ imply ICH_SPI
+ imply INTEL_ICH6_GPIO
+ imply SCSI
+ imply SPI_FLASH
+ imply SYS_NS16550
+ imply USB
+ imply USB_EHCI_HCD
+ imply USB_XHCI_HCD
+ #imply VIDEO_VESA
+
+if INTEL_BROADWELL_DE
+
+config FSP_ADDR
+ hex
+ default 0xffeb0000
+
+#config DCACHE_RAM_BASE
+# default 0xfef00000
+
+#config DCACHE_RAM_SIZE
+# default 0x4000
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select SMM_TSEG
+ #select X86_RAMTEST
+
+config SMM_TSEG_SIZE
+ hex
+ default 0x800000
+
+config INTERNAL_UART
+ bool
+ default y
+
+config MAX_CPUS
+ int
+ default 16
+
+config MAX_PIRQ_LINKS
+ int
+ default 4
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config XIP_ROM_SIZE
+ hex
+ default 0x10000
+
+endif
diff --git a/arch/x86/cpu/broadwell-de/Makefile b/arch/x86/cpu/broadwell-de/Makefile
new file mode 100644
index 0000000000..0fa427e1bf
--- /dev/null
+++ b/arch/x86/cpu/broadwell-de/Makefile
@@ -0,0 +1,10 @@ 
+#
+# Copyright (C) 2017, Vincenzo Bove <vincenzo.bove@prodrive-technologies.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += fsp_configs.o
+obj-y += broadwell_de.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
diff --git a/arch/x86/cpu/broadwell-de/acpi.c b/arch/x86/cpu/broadwell-de/acpi.c
new file mode 100644
index 0000000000..2e005623de
--- /dev/null
+++ b/arch/x86/cpu/broadwell-de/acpi.c
@@ -0,0 +1,234 @@ 
+/*
+ * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove@prodrive-technologies.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <asm/acpi_s3.h>
+#include <asm/acpi_table.h>
+#include <asm/io.h>
+#include <asm/tables.h>
+#include <asm/arch/global_nvs.h>
+#include <asm/arch/iomap.h>
+
+#define PM1_STS 0x00
+#define PM1_CNT 0x04
+#define GEN_PMCON1 0xA0
+#define WAK_STS     (1 << 15)
+#define PWR_FLR (1 << 1)
+#define  SUS_PWR_FLR (1 << 14)
+
+#define PMC_BASE_ADDRESS 0xfed03000
+#define PMC_BASE_SIZE 0x400
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+       void *dsdt)
+{
+ struct acpi_table_header *header = &(fadt->header);
+ u16 pmbase = ACPI_BASE_ADDRESS;
+
+ memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+
+ /*
+ * Reference section 5.2.9 Fixed ACPI Description Table (FADT)
+ * in the ACPI 3.0b specification.
+ */
+
+ /* FADT Header Structure */
+ acpi_fill_header(header, "FACP");
+ header->length = sizeof(struct acpi_fadt);
+ header->revision = 4;
+
+ /* ACPI Pointers */
+ fadt->firmware_ctrl = (u32)facs;
+ fadt->dsdt = (u32)dsdt;
+
+ fadt->preferred_pm_profile = ACPI_PM_MOBILE;
+ fadt->sci_int = 9;
+
+ /* System Management */
+ fadt->smi_cmd = 0;
+ fadt->acpi_enable = 0;
+ fadt->acpi_disable = 0;
+
+ /* Power Control */
+ fadt->s4bios_req = 0;
+ fadt->pstate_cnt = 0;
+
+ /* Control Registers - Base Address */
+ fadt->pm1a_evt_blk = pmbase + 0x00; //PM1_STS
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x04; //PM1_CNT
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50; //PM2A_CNT_BLK
+ fadt->pm_tmr_blk = pmbase + 0x8; //PM1_TMR
+ fadt->gpe0_blk = pmbase + 0x20; //GPE0_STS
+ fadt->gpe1_blk = 0;
+
+ /* Control Registers - Length */
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 8;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+ fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 0;
+
+ /* RTC Registers */
+ fadt->day_alrm = 0x0d;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
+ ACPI_FADT_PLATFORM_CLOCK;
+
+ /* Reset Register */
+ fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->reset_reg.addrl = IO_PORT_RESET;
+ fadt->reset_reg.addrh = 0;
+ fadt->reset_value = 6; //SYS_RST | RST_CPU | FULL_RST
+
+ /* Extended ACPI Pointers */
+ fadt->x_firmware_ctl_l = (u32)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (u32)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ /* PM1 Status & PM1 Enable */
+ fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.access_size = 0;
+ fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ /* PM1 Control Registers */
+ fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+ fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.access_size = 0;
+ fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ /* PM2 Control Registers */
+ fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ /* PM1 Timer Register */
+ fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ /*  General-Purpose Event Registers */
+ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_gpe0_blk.bit_width = 64;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.access_size = 0;
+ fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
+{
+ struct udevice *dev;
+ int ret;
+
+ /* at least we have one processor */
+ gnvs->pcnt = 1;
+ /* override the processor count with actual number */
+ ret = uclass_find_first_device(UCLASS_CPU, &dev);
+ if (ret == 0 && dev != NULL) {
+ ret = cpu_get_count(dev);
+ if (ret > 0)
+ gnvs->pcnt = ret;
+ }
+
+ /* determine whether internal uart is on */
+ if (IS_ENABLED(CONFIG_INTERNAL_UART))
+ gnvs->iuart_en = 1;
+ else
+ gnvs->iuart_en = 0;
+}
+
+#ifdef CONFIG_HAVE_ACPI_RESUME
+
+enum acpi_sleep_state chipset_prev_sleep_state(void)
+{
+ u32 pm1_sts;
+ u32 pm1_cnt;
+ u32 gen_pmcon1;
+ enum acpi_sleep_state prev_sleep_state = ACPI_S0;
+
+ /* Read Power State */
+ pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
+ pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+ gen_pmcon1 = readl(PMC_BASE_ADDRESS + GEN_PMCON1);
+
+ debug("PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n",
+       pm1_sts, pm1_cnt, gen_pmcon1);
+
+ if (pm1_sts & WAK_STS)
+ prev_sleep_state = acpi_sleep_from_pm1(pm1_cnt);
+
+ if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR))
+ prev_sleep_state = ACPI_S5;
+
+ return prev_sleep_state;
+}
+
+void chipset_clear_sleep_state(void)
+{
+ u32 pm1_cnt;
+
+ pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+ outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
+}
+
+#endif
diff --git a/arch/x86/cpu/broadwell-de/broadwell_de.c b/arch/x86/cpu/broadwell-de/broadwell_de.c
new file mode 100644
index 0000000000..54afde7db9
--- /dev/null
+++ b/arch/x86/cpu/broadwell-de/broadwell_de.c
@@ -0,0 +1,38 @@ 
+/*
+ * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove@prodrive-technologies.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mrccache.h>
+#include <asm/post.h>
+
+int arch_cpu_init(void)
+{
+ post_code(POST_CPU_INIT);
+
+ return x86_cpu_init_f();
+}
+
+int arch_misc_init(void)
+{
+#ifdef CONFIG_ENABLE_MRC_CACHE
+ /*
+ * We intend not to check any return value here, as even MRC cache
+ * is not saved successfully, it is not a severe error that will
+ * prevent system from continuing to boot.
+ */
+ mrccache_save();
+#endif
+
+ return 0;
+}
+
+
+
+void reset_cpu(ulong addr)
+{
+ /* cold reset */
+ x86_full_reset();
+}
diff --git a/arch/x86/cpu/broadwell-de/cpu.c b/arch/x86/cpu/broadwell-de/cpu.c
new file mode 100644
index 0000000000..71377fad1c
--- /dev/null
+++ b/arch/x86/cpu/broadwell-de/cpu.c
@@ -0,0 +1,98 @@ 
+/*
+ * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove@prodrive-technologies.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <cpu.h>
+#include <pci.h>
+#include <asm/cpu.h>
+#include <asm/cpu_x86.h>
+#include <asm/cpu_common.h>
+#include <asm/intel_regs.h>
+#include <asm/io.h>
+#include <asm/msr.h>
+#include <asm/post.h>
+#include <asm/turbo.h>
+#include <asm/mrccache.h>
+#include <asm/lapic.h>
+
+#define MSR_CORE_THREAD_COUNT 0x35
+
+static void configure_mca(void)
+{
+ msr_t msr;
+ const unsigned int mcg_cap_msr = 0x179;
+ int i;
+ int num_banks;
+
+ msr = msr_read(mcg_cap_msr);
+ num_banks = msr.lo & 0xff;
+ msr.lo = 0;
+ msr.hi = 0;
+ /*
+ * TODO(adurbin): This should only be done on a cold boot. Also, some
+ * of these banks are core vs package scope. For now every CPU clears
+ * every bank
+ */
+ for (i = 0; i < num_banks; i++) {
+ msr_write(MSR_IA32_MC0_STATUS + (i * 4) + 1, msr);
+ msr_write(MSR_IA32_MC0_STATUS + (i * 4) + 2, msr);
+ msr_write(MSR_IA32_MC0_STATUS + (i * 4) + 3, msr);
+
+ }
+
+ msr.lo = 0xffffffff;
+ msr.hi = 0xffffffff;
+
+ for (i = 0; i < num_banks; i++) {
+ msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
+ }
+}
+
+static int cpu_x86_broadwell_de_probe(struct udevice *dev)
+{
+ debug("Init Broadwell-DE core\n");
+
+ /* Clear out pending MCEs */
+ configure_mca();
+
+ return 0;
+}
+
+
+static int broadwell_de_get_info(struct udevice *dev, struct cpu_info *info)
+{
+ //TBD
+
+    return 0;
+}
+
+static int broadwell_de_get_count(struct udevice *dev)
+{
+ msr_t core_thread_count = msr_read(MSR_CORE_THREAD_COUNT);
+ return core_thread_count.lo & 0xffff;
+}
+
+static const struct cpu_ops cpu_x86_broadwell_de_ops = {
+ .get_desc = cpu_x86_get_desc,
+ .get_info = broadwell_de_get_info,
+ .get_count = broadwell_de_get_count,
+ .get_vendor = cpu_x86_get_vendor,
+};
+
+static const struct udevice_id cpu_x86_broadwell_de_ids[] = {
+ { .compatible = "intel,broadwell-de-cpu" },
+ { }
+};
+
+U_BOOT_DRIVER(cpu_x86_broadwell_de_drv) = {
+ .name = "cpu_x86_broadwell_de",
+ .id = UCLASS_CPU,
+ .of_match = cpu_x86_broadwell_de_ids,
+ .bind = cpu_x86_bind,
+ .probe = cpu_x86_broadwell_de_probe,
+ .ops = &cpu_x86_broadwell_de_ops,
+};
diff --git a/arch/x86/cpu/broadwell-de/fsp_configs.c b/arch/x86/cpu/broadwell-de/fsp_configs.c
new file mode 100644
index 0000000000..b2ccbdbd55
--- /dev/null
+++ b/arch/x86/cpu/broadwell-de/fsp_configs.c
@@ -0,0 +1,292 @@ 
+/*
+ * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove@prodrive-technologies.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * Override the FSP's configuration data.
+ * If the device tree does not specify an integer setting, use the default
+ * provided by Prodrive BroadwellDE.rom
+ */
+void update_fsp_configs(struct fsp_config_data *config,
+ struct fspinit_rtbuf *rt_buf)
+{
+ struct upd_region *fsp_upd = &config->fsp_upd;
+ const void *blob = gd->fdt_blob;
+ int node;
+
+ /* Initialize runtime buffer for fsp_init() */
+ rt_buf->common.stack_top = config->common.stack_top - 32;
+ rt_buf->common.boot_mode = config->common.boot_mode;
+ rt_buf->common.upd_data = &config->fsp_upd;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BROADWELL_DE_FSP);
+ if (node < 0) {
+ debug("%s: Cannot find FSP node\n", __func__);
+ return;
+ }
+
+  fsp_upd->memEccSupport = fdtdec_get_int(blob, node,
+                      "fsp,memEccSupport",
+                       MEM_ECC_SUPPORT_AUTO);
+
+ fsp_upd->memDdrMemoryType = fdtdec_get_int(blob, node,
+                      "fsp,memDdrMemoryType",
+                      MEM_DDR_MEMORY_TYPE_UDIMM_AND_RDIMM);
+
+  fsp_upd->memRankMultiplication = fdtdec_get_int(blob, node,
+                      "fsp,memRankMultiplication",
+                      MEM_RANK_MULTIPLICATION_AUTO);
+
+  fsp_upd->memRankMarginTool = fdtdec_get_int(blob, node,
+                      "fsp,memRankMarginTool",
+                      MEM_RANK_MARGIN_TOOL_AUTO);
+
+  fsp_upd->memScrambling = fdtdec_get_int(blob, node,
+                      "fsp,memScrambling",
+                      MEM_SCRAMBLING_AUTO);
+
+  fsp_upd->memRefreshMode = fdtdec_get_int(blob, node,
+                      "fsp,memRefreshMode",
+                      MEM_REFRESH_MODE_ACC_SELF_REFRESH);
+
+  fsp_upd->memMcOdtOverride = fdtdec_get_int(blob, node,
+                      "fsp,memMcOdtOverride",
+                      MEM_MC0DT_OVERRIDE_AUTO);
+
+  fsp_upd->memCAParity = fdtdec_get_int(blob, node,
+                      "fsp,memCAParity",
+                      MEM_CA_PARITY_AUTO);
+
+  fsp_upd->memThermalThrottling = fdtdec_get_int(blob, node,
+                      "fsp,memThermalThrottling",
+                      MEM_THERMAL_THROTTLING_CLOSEDLOOP);
+
+  fsp_upd->memPowerSavingsMode = fdtdec_get_int(blob, node,
+                      "fsp,memPowerSavingsMode",
+                      MEM_POWER_SAVINGS_MODE_AUTO);
+
+  fsp_upd->memElectricalThrottling = fdtdec_get_int(blob, node,
+                      "fsp,memElectricalThrottling",
+                      MEM_ELECTRICAL_THROTTLING_DISABLED);
+
+  fsp_upd->memPagePolicy = fdtdec_get_int(blob, node,
+                      "fsp,memPagePolicy",
+                      MEM_PAGE_POLICY_AUTO);
+
+  fsp_upd->memSocketInterleaveBelow4G = fdtdec_get_int(blob, node,
+                      "fsp,memSocketInterleaveBelow4G",
+                      MEM_SOCKET_INTERLEAVE_BELOW_4G_DISABLED);
+
+  fsp_upd->memChannelInterleave = fdtdec_get_int(blob, node,
+                      "fsp,memChannelInterleave",
+                      MEM_CHANNEL_INTERLEAVE_AUTO);
+
+  fsp_upd->memRankInterleave = fdtdec_get_int(blob, node,
+                      "fsp,memRankInterleave",
+                      MEM_RANK_INTERLEAVE_AUTO);
+
+  #ifdef CONFIG_FSP_MEMORY_DOWN
+    fsp_upd->memDownEnable = fdtdec_get_bool(blob, node, "fsp,memDownEnable");
+
+ fsp_upd->memDownCh0Dimm0SpdPtr = fdtdec_get_int(blob, node,
+                      "fsp,memDownCh0Dimm0SpdPtr",
+                      CONFIG_SPD_ADDR);
+
+    fsp_upd->memDownCh0Dimm1SpdPtr = fdtdec_get_int(blob, node,
+                      "fsp,memDownCh0Dimm1SpdPtr",
+                      0x0);
+
+    fsp_upd->memDownCh1Dimm0SpdPtr = fdtdec_get_int(blob, node,
+                      "fsp,memDownCh1Dimm0SpdPtr",
+                      0x0);
+
+    fsp_upd->memDownCh1Dimm1SpdPtr = fdtdec_get_int(blob, node,
+                      "fsp,memDownCh1Dimm1SpdPtr",
+                      0x0);
+  #endif
+
+  //#ifdef CONFIG_ENABLE_MRC_CACHE
+    //fsp_upd->memFastBoot = fdtdec_get_int(blob, node, "fsp,mem-fast-boot", MEM_FAST_BOOT_ENABLE);
+  //#else
+    //fsp_upd->memFastBoot = fdtdec_get_int(blob, node, "fsp,mem-fast-boot", MEM_FAST_BOOT_DISABLE);
+  //#endif
+  fsp_upd->memFastBoot = fdtdec_get_int(blob, node, "fsp,mem-fast-boot", MEM_FAST_BOOT_DISABLE);
+
+ fsp_upd->pam0_hienable = fdtdec_get_int(blob, node,
+                      "fsp,pam0-hienable",
+                      PAM_RW_DRAM_ONLY);
+
+ fsp_upd->pam1_loenable = fdtdec_get_int(blob, node,
+                      "fsp,pam1-loenable",
+                      PAM_RW_DRAM_ONLY);
+
+ fsp_upd->pam1_hienable = fdtdec_get_int(blob, node,
+                      "fsp,pam1-hienable",
+                      PAM_RW_DRAM_ONLY);
+
+ fsp_upd->pam2_loenable = fdtdec_get_int(blob, node,
+                      "fsp,pam2-loenable",
+                      PAM_RW_DRAM_ONLY);
+
+ fsp_upd->pam2_hienable = fdtdec_get_int(blob, node,
+                      "fsp,pam2-hienable",
+                      PAM_RW_DRAM_ONLY);
+
+ fsp_upd->pam3_loenable = fdtdec_get_int(blob, node,
+                      "fsp,pam3-loenable",
+                      PAM_RW_DRAM_ONLY);
+
+ fsp_upd->pam3_hienable = fdtdec_get_int(blob, node,
+                      "fsp,pam3-hienable",
+                      PAM_RW_DRAM_ONLY);
+
+ fsp_upd->pam4_loenable = fdtdec_get_int(blob, node,
+                      "fsp,pam4-loenable",
+                      PAM_RW_DRAM_ONLY);
+
+ fsp_upd->pam4_hienable = fdtdec_get_int(blob, node,
+                      "fsp,pam4-hienable",
+                      PAM_RW_DRAM_ONLY);
+
+ fsp_upd->pam5_loenable = fdtdec_get_int(blob, node,
+                      "fsp,pam5-loenable",
+                      PAM_RW_DRAM_ONLY);
+
+ fsp_upd->pam5_hienable = fdtdec_get_int(blob, node,
+                      "fsp,pam5-hienable",
+                      PAM_RW_DRAM_ONLY);
+
+ fsp_upd->pam6_loenable = fdtdec_get_int(blob, node,
+                      "fsp,pam6-loenable",
+                      PAM_RW_DRAM_ONLY);
+
+ fsp_upd->pam6_hienable = fdtdec_get_int(blob, node,
+                      "fsp,pam6-hienable",
+                      PAM_RW_DRAM_ONLY);
+
+  fsp_upd->memAdr = fdtdec_get_int(blob, node,
+                      "fsp,memAdr",
+                      MEM_ADR_DISABLED);
+
+ fsp_upd->serialPortType = fdtdec_get_int(blob, node,
+                      "fsp,serial-port-type",
+                      SERIAL_PORT_TYPE_IO);
+
+  fsp_upd->serialPortAddress = fdtdec_get_int(blob, node,
+                      "fsp,serial-port-address",
+                      0x3f8);
+
+  fsp_upd->serialPortConfigure = fdtdec_get_bool(blob, node, "fsp,serial-port-configure");
+
+  fsp_upd->serialPortBaudRate = fdtdec_get_int(blob, node,
+                      "fsp,serial-port-baudrate",
+                      SERIAL_PORT_BAUDRATE_115200);
+
+  fsp_upd->serialPortControllerInit0 = fdtdec_get_bool(blob, node, "fsp,serial-port-controller-init0");
+
+  fsp_upd->serialPortControllerInit1 = fdtdec_get_bool(blob, node, "fsp,serial-port-controller-init1");
+
+  fsp_upd->configIOU1_PciPort3 = fdtdec_get_int(blob, node,
+                      "fsp,config-iou1-pci-port3",
+                      CONFIG_IOU1_PCI_PORT3_X4X4X4X4);
+
+  fsp_upd->configIOU2_PciPort1 = fdtdec_get_int(blob, node,
+                      "fsp,config-iou2-pci-port1",
+                      CONFIG_IOU2_PCI_PORT1_XXX8);
+
+  fsp_upd->pchPciPort1 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port1");
+
+  fsp_upd->pchPciPort2 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port2");
+
+  fsp_upd->pchPciPort3 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port3");
+
+  fsp_upd->pchPciPort4 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port4");
+
+  fsp_upd->pchPciPort5 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port5");
+
+  fsp_upd->pchPciPort6 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port6");
+
+  fsp_upd->pchPciPort7 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port7");
+
+  fsp_upd->pchPciPort8 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port8");
+
+ fsp_upd->ehci1Enable = fdtdec_get_bool(blob, node, "fsp,ehci1-enable");
+
+  fsp_upd->hyperThreading = fdtdec_get_bool(blob, node, "fsp,hyper-threading");
+
+  fsp_upd->debugOutputLevel = fdtdec_get_int(blob, node,
+                        "fsp,debug-output-level",
+                        DEBUG_OUTPUT_LEVEL_NORMAL);
+
+  fsp_upd->tcoTimerHaltLock = fdtdec_get_bool(blob, node, "fsp,tco-timer-halt-lock");
+
+  fsp_upd->turboMode = fdtdec_get_bool(blob, node, "fsp,turbo-mode");
+
+  fsp_upd->bootPerfMode = fdtdec_get_bool(blob, node, "fsp,boot-perf-mode");
+
+  fsp_upd->pciePort1aAspm = fdtdec_get_int(blob, node,
+                          "fsp,pcie-port1a-aspm",
+                          PCIE_ASPM_DISABLED);
+
+  fsp_upd->pciePort1bAspm = fdtdec_get_int(blob, node,
+                          "fsp,pcie-port1b-aspm",
+                          PCIE_ASPM_DISABLED);
+
+  fsp_upd->pciePort3aAspm = fdtdec_get_int(blob, node,
+                          "fsp,pcie-port3a-aspm",
+                          PCIE_ASPM_DISABLED);
+
+ fsp_upd->pciePort3bAspm = fdtdec_get_int(blob, node,
+                          "fsp,pcie-port3b-aspm",
+                          PCIE_ASPM_DISABLED);
+
+ fsp_upd->pciePort3cAspm = fdtdec_get_int(blob, node,
+                          "fsp,pcie-port3c-aspm",
+                          PCIE_ASPM_DISABLED);
+
+ fsp_upd->pciePort3dAspm = fdtdec_get_int(blob, node,
+                          "fsp,pcie-port3d-aspm",
+                          PCIE_ASPM_DISABLED);
+
+  fsp_upd->pchPciePort1Aspm = fdtdec_get_int(blob, node,
+                          "fsp,pch-pcie-port1-aspm",
+                          PCH_PCI_ASPM_DISABLED);
+
+  fsp_upd->pchPciePort2Aspm = fdtdec_get_int(blob, node,
+                          "fsp,pch-pcie-port2-aspm",
+                          PCH_PCI_ASPM_DISABLED);
+
+ fsp_upd->pchPciePort3Aspm = fdtdec_get_int(blob, node,
+                          "fsp,pch-pcie-port3-aspm",
+                          PCH_PCI_ASPM_DISABLED);
+
+ fsp_upd->pchPciePort4Aspm = fdtdec_get_int(blob, node,
+                          "fsp,pch-pcie-port4-aspm",
+                          PCH_PCI_ASPM_DISABLED);
+
+ fsp_upd->pchPciePort5Aspm = fdtdec_get_int(blob, node,
+                          "fsp,pch-pcie-port5-aspm",
+                          PCH_PCI_ASPM_DISABLED);
+
+ fsp_upd->pchPciePort6Aspm = fdtdec_get_int(blob, node,
+                          "fsp,pch-pcie-port6-aspm",
+                          PCH_PCI_ASPM_DISABLED);
+
+ fsp_upd->pchPciePort7Aspm = fdtdec_get_int(blob, node,
+                          "fsp,pch-pcie-port7-aspm",
+                          PCH_PCI_ASPM_DISABLED);
+
+ fsp_upd->pchPciePort8Aspm = fdtdec_get_int(blob, node,
+                          "fsp,pch-pcie-port8-aspm",
+                          PCH_PCI_ASPM_DISABLED);
+
+  fsp_upd->thermalDeviceEnable = fdtdec_get_bool(blob, node, "fsp,thermal-device-enable");
+}