@@ -7,6 +7,7 @@ Required properties:
or
"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
"fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
+ "fsl,ls2080a-qspi" followed by "fsl,ls1088a-qspi",
- reg : the first contains the register location and length,
the second contains the memory mapping address and length
- reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
@@ -94,6 +94,27 @@
};
};
+&qspi {
+ status = "okay";
+ fsl,qspi-has-second-chip;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ qflash0: s25fs512s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+
+ qflash1: s25fs512s@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <1>;
+ };
+
+};
+
&ifc {
ranges = <0 0 0x5 0x30000000 0x00010000
2 0 0x5 0x20000000 0x00010000>;
@@ -394,6 +394,18 @@
status = "disabled";
};
+ qspi: quadspi@20c0000 {
+ compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c0000 0x0 0x10000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <0 25 0x4>; /* Level high type */
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "qspi_en", "qspi";
+ };
+
sata: sata@3200000 {
compatible = "fsl,ls1088a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>,