| Message ID | 92d3f3362e407e1c5fba761b5e869b52986ef199.1516330237.git-series.andrew.donnellan@au1.ibm.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Initial OpenCAPI 3.0 Support for P9 | expand |
Le 19/01/2018 à 03:50, Andrew Donnellan a écrit : > Split out common helper functions for NPU register access into a separate > file, as these will be used extensively by both NVLink and OpenCAPI code. > > Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> > > --- Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> > v1->v2: > > - Add copyright header (Fred) > --- > hw/Makefile.inc | 2 +- > hw/npu2-common.c | 114 +++++++++++++++++++++++++++++++++++++++++++++- > hw/npu2.c | 92 +------------------------------------ > include/npu2-regs.h | 5 ++- > include/npu2.h | 2 +- > 5 files changed, 122 insertions(+), 93 deletions(-) > create mode 100644 hw/npu2-common.c > > diff --git a/hw/Makefile.inc b/hw/Makefile.inc > index 04cacd1..cf8649d 100644 > --- a/hw/Makefile.inc > +++ b/hw/Makefile.inc > @@ -7,7 +7,7 @@ HW_OBJS += p7ioc.o p7ioc-inits.o p7ioc-phb.o > HW_OBJS += phb3.o sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o > HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o > HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o > -HW_OBJS += phys-map.o sbe-p9.o capp.o occ-sensor.o vas.o > +HW_OBJS += npu2-common.o phys-map.o sbe-p9.o capp.o occ-sensor.o vas.o > HW=hw/built-in.o > > # FIXME hack this for now > diff --git a/hw/npu2-common.c b/hw/npu2-common.c > new file mode 100644 > index 0000000..0c22d61 > --- /dev/null > +++ b/hw/npu2-common.c > @@ -0,0 +1,114 @@ > +/* Copyright 2013-2018 IBM Corp. > + * > + * Licensed under the Apache License, Version 2.0 (the "License"); > + * you may not use this file except in compliance with the License. > + * You may obtain a copy of the License at > + * > + * http://www.apache.org/licenses/LICENSE-2.0 > + * > + * Unless required by applicable law or agreed to in writing, software > + * distributed under the License is distributed on an "AS IS" BASIS, > + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or > + * implied. > + * See the License for the specific language governing permissions and > + * limitations under the License. > + */ > + > +#include <skiboot.h> > +#include <xscom.h> > +#include <pci.h> > +#include <npu2.h> > +#include <npu2-regs.h> > +#include <bitutils.h> > + > +bool is_p9dd1(void) > +{ > + struct proc_chip *chip = next_chip(NULL); > + > + return chip && > + (chip->type == PROC_CHIP_P9_NIMBUS || > + chip->type == PROC_CHIP_P9_CUMULUS) && > + (chip->ec_level & 0xf0) == 0x10; > +} > + > +/* > + * We use the indirect method because it uses the same addresses as > + * the MMIO offsets (NPU RING) > + */ > +static void npu2_scom_set_addr(uint64_t gcid, uint64_t scom_base, > + uint64_t addr, uint64_t size) > +{ > + uint64_t isa = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_ADDR : > + NPU2_MISC_SCOM_IND_SCOM_ADDR; > + > + addr = SETFIELD(NPU2_MISC_DA_ADDR, 0ull, addr); > + addr = SETFIELD(NPU2_MISC_DA_LEN, addr, size); > + xscom_write(gcid, scom_base + isa, addr); > +} > + > +void npu2_scom_write(uint64_t gcid, uint64_t scom_base, > + uint64_t reg, uint64_t size, > + uint64_t val) > +{ > + uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : > + NPU2_MISC_SCOM_IND_SCOM_DATA; > + > + npu2_scom_set_addr(gcid, scom_base, reg, size); > + xscom_write(gcid, scom_base + isd, val); > +} > + > +uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base, > + uint64_t reg, uint64_t size) > +{ > + uint64_t val; > + uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : > + NPU2_MISC_SCOM_IND_SCOM_DATA; > + > + npu2_scom_set_addr(gcid, scom_base, reg, size); > + xscom_read(gcid, scom_base + isd, &val); > + > + return val; > +} > + > +void npu2_write_4b(struct npu2 *p, uint64_t reg, uint32_t val) > +{ > + npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B, > + (uint64_t)val << 32); > +} > + > +uint32_t npu2_read_4b(struct npu2 *p, uint64_t reg) > +{ > + return npu2_scom_read(p->chip_id, p->xscom_base, reg, > + NPU2_MISC_DA_LEN_4B) >> 32; > +} > + > +void npu2_write(struct npu2 *p, uint64_t reg, uint64_t val) > +{ > + npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, val); > +} > + > +uint64_t npu2_read(struct npu2 *p, uint64_t reg) > +{ > + return npu2_scom_read(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B); > +} > + > +void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask) > +{ > + uint64_t new_val; > + > + new_val = npu2_read(p, reg); > + new_val &= ~mask; > + new_val |= val & mask; > + npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, new_val); > +} > + > +void npu2_write_mask_4b(struct npu2 *p, uint64_t reg, uint32_t val, uint32_t mask) > +{ > + uint32_t new_val; > + > + new_val = npu2_read_4b(p, reg); > + new_val &= ~mask; > + new_val |= val & mask; > + npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B, > + (uint64_t)new_val << 32); > +} > diff --git a/hw/npu2.c b/hw/npu2.c > index c88394b..41c30f4 100644 > --- a/hw/npu2.c > +++ b/hw/npu2.c > @@ -64,98 +64,6 @@ > * configure one particular BAR. > */ > > -static bool is_p9dd1(void) > -{ > - struct proc_chip *chip = next_chip(NULL); > - > - return chip && > - (chip->type == PROC_CHIP_P9_NIMBUS || > - chip->type == PROC_CHIP_P9_CUMULUS) && > - (chip->ec_level & 0xf0) == 0x10; > -} > - > -/* > - * We use the indirect method because it uses the same addresses as > - * the MMIO offsets (NPU RING) > - */ > -static void npu2_scom_set_addr(uint64_t gcid, uint64_t scom_base, > - uint64_t addr, uint64_t size) > -{ > - uint64_t isa = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_ADDR : > - NPU2_MISC_SCOM_IND_SCOM_ADDR; > - > - addr = SETFIELD(NPU2_MISC_DA_ADDR, 0ull, addr); > - addr = SETFIELD(NPU2_MISC_DA_LEN, addr, size); > - xscom_write(gcid, scom_base + isa, addr); > -} > - > -static void npu2_scom_write(uint64_t gcid, uint64_t scom_base, > - uint64_t reg, uint64_t size, > - uint64_t val) > -{ > - uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : > - NPU2_MISC_SCOM_IND_SCOM_DATA; > - > - npu2_scom_set_addr(gcid, scom_base, reg, size); > - xscom_write(gcid, scom_base + isd, val); > -} > - > -static uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base, > - uint64_t reg, uint64_t size) > -{ > - uint64_t val; > - uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : > - NPU2_MISC_SCOM_IND_SCOM_DATA; > - > - npu2_scom_set_addr(gcid, scom_base, reg, size); > - xscom_read(gcid, scom_base + isd, &val); > - > - return val; > -} > - > -void npu2_write_4b(struct npu2 *p, uint64_t reg, uint32_t val) > -{ > - npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B, > - (uint64_t)val << 32); > -} > - > -uint32_t npu2_read_4b(struct npu2 *p, uint64_t reg) > -{ > - return npu2_scom_read(p->chip_id, p->xscom_base, reg, > - NPU2_MISC_DA_LEN_4B) >> 32; > -} > - > -void npu2_write(struct npu2 *p, uint64_t reg, uint64_t val) > -{ > - npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, val); > -} > - > -uint64_t npu2_read(struct npu2 *p, uint64_t reg) > -{ > - return npu2_scom_read(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B); > -} > - > -void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask) > -{ > - uint64_t new_val; > - > - new_val = npu2_read(p, reg); > - new_val &= ~mask; > - new_val |= val & mask; > - npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, new_val); > -} > - > -void npu2_write_mask_4b(struct npu2 *p, uint64_t reg, uint32_t val, uint32_t mask) > -{ > - uint32_t new_val; > - > - new_val = npu2_read_4b(p, reg); > - new_val &= ~mask; > - new_val |= val & mask; > - npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B, > - (uint64_t)new_val << 32); > -} > - > /* Set a specific flag in the vendor config space */ > void npu2_set_link_flag(struct npu2_dev *ndev, uint8_t flag) > { > diff --git a/include/npu2-regs.h b/include/npu2-regs.h > index e739ac5..b190d0f 100644 > --- a/include/npu2-regs.h > +++ b/include/npu2-regs.h > @@ -23,6 +23,11 @@ void npu2_write4(struct npu2 *p, uint64_t reg, uint64_t val); > uint64_t npu2_read(struct npu2 *p, uint64_t reg); > void npu2_write(struct npu2 *p, uint64_t reg, uint64_t val); > void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); > +uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base, > + uint64_t reg, uint64_t size); > +void npu2_scom_write(uint64_t gcid, uint64_t scom_base, > + uint64_t reg, uint64_t size, > + uint64_t val); > > /* These aren't really NPU specific registers but we initialise them in NPU > * code */ > diff --git a/include/npu2.h b/include/npu2.h > index dae152a..d0c9ac5 100644 > --- a/include/npu2.h > +++ b/include/npu2.h > @@ -163,4 +163,6 @@ void npu2_dev_procedure_reset(struct npu2_dev *dev); > void npu2_set_link_flag(struct npu2_dev *ndev, uint8_t flag); > void npu2_clear_link_flag(struct npu2_dev *ndev, uint8_t flag); > extern int nv_zcal_nominal; > +bool is_p9dd1(void); > + > #endif /* __NPU2_H */ >
diff --git a/hw/Makefile.inc b/hw/Makefile.inc index 04cacd1..cf8649d 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -7,7 +7,7 @@ HW_OBJS += p7ioc.o p7ioc-inits.o p7ioc-phb.o HW_OBJS += phb3.o sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o -HW_OBJS += phys-map.o sbe-p9.o capp.o occ-sensor.o vas.o +HW_OBJS += npu2-common.o phys-map.o sbe-p9.o capp.o occ-sensor.o vas.o HW=hw/built-in.o # FIXME hack this for now diff --git a/hw/npu2-common.c b/hw/npu2-common.c new file mode 100644 index 0000000..0c22d61 --- /dev/null +++ b/hw/npu2-common.c @@ -0,0 +1,114 @@ +/* Copyright 2013-2018 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include <skiboot.h> +#include <xscom.h> +#include <pci.h> +#include <npu2.h> +#include <npu2-regs.h> +#include <bitutils.h> + +bool is_p9dd1(void) +{ + struct proc_chip *chip = next_chip(NULL); + + return chip && + (chip->type == PROC_CHIP_P9_NIMBUS || + chip->type == PROC_CHIP_P9_CUMULUS) && + (chip->ec_level & 0xf0) == 0x10; +} + +/* + * We use the indirect method because it uses the same addresses as + * the MMIO offsets (NPU RING) + */ +static void npu2_scom_set_addr(uint64_t gcid, uint64_t scom_base, + uint64_t addr, uint64_t size) +{ + uint64_t isa = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_ADDR : + NPU2_MISC_SCOM_IND_SCOM_ADDR; + + addr = SETFIELD(NPU2_MISC_DA_ADDR, 0ull, addr); + addr = SETFIELD(NPU2_MISC_DA_LEN, addr, size); + xscom_write(gcid, scom_base + isa, addr); +} + +void npu2_scom_write(uint64_t gcid, uint64_t scom_base, + uint64_t reg, uint64_t size, + uint64_t val) +{ + uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : + NPU2_MISC_SCOM_IND_SCOM_DATA; + + npu2_scom_set_addr(gcid, scom_base, reg, size); + xscom_write(gcid, scom_base + isd, val); +} + +uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base, + uint64_t reg, uint64_t size) +{ + uint64_t val; + uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : + NPU2_MISC_SCOM_IND_SCOM_DATA; + + npu2_scom_set_addr(gcid, scom_base, reg, size); + xscom_read(gcid, scom_base + isd, &val); + + return val; +} + +void npu2_write_4b(struct npu2 *p, uint64_t reg, uint32_t val) +{ + npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B, + (uint64_t)val << 32); +} + +uint32_t npu2_read_4b(struct npu2 *p, uint64_t reg) +{ + return npu2_scom_read(p->chip_id, p->xscom_base, reg, + NPU2_MISC_DA_LEN_4B) >> 32; +} + +void npu2_write(struct npu2 *p, uint64_t reg, uint64_t val) +{ + npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, val); +} + +uint64_t npu2_read(struct npu2 *p, uint64_t reg) +{ + return npu2_scom_read(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B); +} + +void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask) +{ + uint64_t new_val; + + new_val = npu2_read(p, reg); + new_val &= ~mask; + new_val |= val & mask; + npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, new_val); +} + +void npu2_write_mask_4b(struct npu2 *p, uint64_t reg, uint32_t val, uint32_t mask) +{ + uint32_t new_val; + + new_val = npu2_read_4b(p, reg); + new_val &= ~mask; + new_val |= val & mask; + npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B, + (uint64_t)new_val << 32); +} diff --git a/hw/npu2.c b/hw/npu2.c index c88394b..41c30f4 100644 --- a/hw/npu2.c +++ b/hw/npu2.c @@ -64,98 +64,6 @@ * configure one particular BAR. */ -static bool is_p9dd1(void) -{ - struct proc_chip *chip = next_chip(NULL); - - return chip && - (chip->type == PROC_CHIP_P9_NIMBUS || - chip->type == PROC_CHIP_P9_CUMULUS) && - (chip->ec_level & 0xf0) == 0x10; -} - -/* - * We use the indirect method because it uses the same addresses as - * the MMIO offsets (NPU RING) - */ -static void npu2_scom_set_addr(uint64_t gcid, uint64_t scom_base, - uint64_t addr, uint64_t size) -{ - uint64_t isa = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_ADDR : - NPU2_MISC_SCOM_IND_SCOM_ADDR; - - addr = SETFIELD(NPU2_MISC_DA_ADDR, 0ull, addr); - addr = SETFIELD(NPU2_MISC_DA_LEN, addr, size); - xscom_write(gcid, scom_base + isa, addr); -} - -static void npu2_scom_write(uint64_t gcid, uint64_t scom_base, - uint64_t reg, uint64_t size, - uint64_t val) -{ - uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : - NPU2_MISC_SCOM_IND_SCOM_DATA; - - npu2_scom_set_addr(gcid, scom_base, reg, size); - xscom_write(gcid, scom_base + isd, val); -} - -static uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base, - uint64_t reg, uint64_t size) -{ - uint64_t val; - uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA : - NPU2_MISC_SCOM_IND_SCOM_DATA; - - npu2_scom_set_addr(gcid, scom_base, reg, size); - xscom_read(gcid, scom_base + isd, &val); - - return val; -} - -void npu2_write_4b(struct npu2 *p, uint64_t reg, uint32_t val) -{ - npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B, - (uint64_t)val << 32); -} - -uint32_t npu2_read_4b(struct npu2 *p, uint64_t reg) -{ - return npu2_scom_read(p->chip_id, p->xscom_base, reg, - NPU2_MISC_DA_LEN_4B) >> 32; -} - -void npu2_write(struct npu2 *p, uint64_t reg, uint64_t val) -{ - npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, val); -} - -uint64_t npu2_read(struct npu2 *p, uint64_t reg) -{ - return npu2_scom_read(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B); -} - -void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask) -{ - uint64_t new_val; - - new_val = npu2_read(p, reg); - new_val &= ~mask; - new_val |= val & mask; - npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, new_val); -} - -void npu2_write_mask_4b(struct npu2 *p, uint64_t reg, uint32_t val, uint32_t mask) -{ - uint32_t new_val; - - new_val = npu2_read_4b(p, reg); - new_val &= ~mask; - new_val |= val & mask; - npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B, - (uint64_t)new_val << 32); -} - /* Set a specific flag in the vendor config space */ void npu2_set_link_flag(struct npu2_dev *ndev, uint8_t flag) { diff --git a/include/npu2-regs.h b/include/npu2-regs.h index e739ac5..b190d0f 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -23,6 +23,11 @@ void npu2_write4(struct npu2 *p, uint64_t reg, uint64_t val); uint64_t npu2_read(struct npu2 *p, uint64_t reg); void npu2_write(struct npu2 *p, uint64_t reg, uint64_t val); void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); +uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base, + uint64_t reg, uint64_t size); +void npu2_scom_write(uint64_t gcid, uint64_t scom_base, + uint64_t reg, uint64_t size, + uint64_t val); /* These aren't really NPU specific registers but we initialise them in NPU * code */ diff --git a/include/npu2.h b/include/npu2.h index dae152a..d0c9ac5 100644 --- a/include/npu2.h +++ b/include/npu2.h @@ -163,4 +163,6 @@ void npu2_dev_procedure_reset(struct npu2_dev *dev); void npu2_set_link_flag(struct npu2_dev *ndev, uint8_t flag); void npu2_clear_link_flag(struct npu2_dev *ndev, uint8_t flag); extern int nv_zcal_nominal; +bool is_p9dd1(void); + #endif /* __NPU2_H */
Split out common helper functions for NPU register access into a separate file, as these will be used extensively by both NVLink and OpenCAPI code. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> --- v1->v2: - Add copyright header (Fred) --- hw/Makefile.inc | 2 +- hw/npu2-common.c | 114 +++++++++++++++++++++++++++++++++++++++++++++- hw/npu2.c | 92 +------------------------------------ include/npu2-regs.h | 5 ++- include/npu2.h | 2 +- 5 files changed, 122 insertions(+), 93 deletions(-) create mode 100644 hw/npu2-common.c