| Message ID | 20180117093448.4102-7-architt@codeaurora.org |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | None | expand |
On Wed, Jan 17, 2018 at 03:04:47PM +0530, Archit Taneja wrote: > Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096). > From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required, > but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names > each PHY revision needs. > > Cc: Rob Herring <robh@kernel.org> > Cc: devicetree@vger.kernel.org > Signed-off-by: Archit Taneja <architt@codeaurora.org> > --- > Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt > index 9c3ad6bbb9f0..26a1796b7145 100644 > --- a/Documentation/devicetree/bindings/display/msm/dsi.txt > +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt > @@ -86,12 +86,19 @@ Required properties: > * "qcom,dsi-phy-28nm-lp" > * "qcom,dsi-phy-20nm" > * "qcom,dsi-phy-28nm-8960" > -- reg: Physical base address and length of the registers of PLL, PHY and PHY > - regulator > + * "qcom,dsi-phy-14nm" > +- reg: Physical base address and length of the registers of PLL, PHY. Some > + revisions require the PHY regulator base address, whereas others require the > + PHY lane base address. See below for each PHY revision. > - reg-names: The names of register regions. The following regions are required: > + For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: > * "dsi_pll" > * "dsi_phy" > * "dsi_phy_regulator" > + For DSI 14nm PHY: > + * "dsi_pll" > + * "dsi_phy" > + * "dsi_phy_lane" > - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating > 2 clocks: A byte clock (index 0), and a pixel clock (index 1). > - power-domains: Should be <&mmcc MDSS_GDSC>. > @@ -102,6 +109,8 @@ Required properties: > - vddio-supply: phandle to vdd-io regulator device node > For 20nm PHY: > - vddio-supply: phandle to vdd-io regulator device node > +- vcca-supply: phandle to vcca regulator device node Did you mean to add this? > + For 14nm PHY: > - vcca-supply: phandle to vcca regulator device node > > Optional properties: > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > hosted by The Linux Foundation > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 01/29/2018 10:45 PM, Rob Herring wrote: > On Wed, Jan 17, 2018 at 03:04:47PM +0530, Archit Taneja wrote: >> Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096). >> From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required, >> but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names >> each PHY revision needs. >> >> Cc: Rob Herring <robh@kernel.org> >> Cc: devicetree@vger.kernel.org >> Signed-off-by: Archit Taneja <architt@codeaurora.org> >> --- >> Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++++++++++-- >> 1 file changed, 11 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt >> index 9c3ad6bbb9f0..26a1796b7145 100644 >> --- a/Documentation/devicetree/bindings/display/msm/dsi.txt >> +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt >> @@ -86,12 +86,19 @@ Required properties: >> * "qcom,dsi-phy-28nm-lp" >> * "qcom,dsi-phy-20nm" >> * "qcom,dsi-phy-28nm-8960" >> -- reg: Physical base address and length of the registers of PLL, PHY and PHY >> - regulator >> + * "qcom,dsi-phy-14nm" >> +- reg: Physical base address and length of the registers of PLL, PHY. Some >> + revisions require the PHY regulator base address, whereas others require the >> + PHY lane base address. See below for each PHY revision. >> - reg-names: The names of register regions. The following regions are required: >> + For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: >> * "dsi_pll" >> * "dsi_phy" >> * "dsi_phy_regulator" >> + For DSI 14nm PHY: >> + * "dsi_pll" >> + * "dsi_phy" >> + * "dsi_phy_lane" >> - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating >> 2 clocks: A byte clock (index 0), and a pixel clock (index 1). >> - power-domains: Should be <&mmcc MDSS_GDSC>. >> @@ -102,6 +109,8 @@ Required properties: >> - vddio-supply: phandle to vdd-io regulator device node >> For 20nm PHY: >> - vddio-supply: phandle to vdd-io regulator device node >> +- vcca-supply: phandle to vcca regulator device node > > Did you mean to add this? Yes, I didn't intend it to be a part of this patch, but this supply is indeed needed for the 20nm PHY. I'll move this to a separate patch. Thanks, Archit > >> + For 14nm PHY: >> - vcca-supply: phandle to vcca regulator device node >> >> Optional properties: >> -- >> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, >> hosted by The Linux Foundation >>
On Wed, Jan 31, 2018 at 1:40 AM, Archit Taneja <architt@codeaurora.org> wrote: > > > On 01/29/2018 10:45 PM, Rob Herring wrote: >> >> On Wed, Jan 17, 2018 at 03:04:47PM +0530, Archit Taneja wrote: >>> >>> Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096). >>> From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required, >>> but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names >>> each PHY revision needs. >>> >>> Cc: Rob Herring <robh@kernel.org> >>> Cc: devicetree@vger.kernel.org >>> Signed-off-by: Archit Taneja <architt@codeaurora.org> >>> --- >>> Documentation/devicetree/bindings/display/msm/dsi.txt | 13 >>> +++++++++++-- >>> 1 file changed, 11 insertions(+), 2 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt >>> b/Documentation/devicetree/bindings/display/msm/dsi.txt >>> index 9c3ad6bbb9f0..26a1796b7145 100644 >>> --- a/Documentation/devicetree/bindings/display/msm/dsi.txt >>> +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt >>> @@ -86,12 +86,19 @@ Required properties: >>> * "qcom,dsi-phy-28nm-lp" >>> * "qcom,dsi-phy-20nm" >>> * "qcom,dsi-phy-28nm-8960" >>> -- reg: Physical base address and length of the registers of PLL, PHY and >>> PHY >>> - regulator >>> + * "qcom,dsi-phy-14nm" >>> +- reg: Physical base address and length of the registers of PLL, PHY. >>> Some >>> + revisions require the PHY regulator base address, whereas others >>> require the >>> + PHY lane base address. See below for each PHY revision. >>> - reg-names: The names of register regions. The following regions are >>> required: >>> + For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: >>> * "dsi_pll" >>> * "dsi_phy" >>> * "dsi_phy_regulator" >>> + For DSI 14nm PHY: >>> + * "dsi_pll" >>> + * "dsi_phy" >>> + * "dsi_phy_lane" >>> - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, >>> creating >>> 2 clocks: A byte clock (index 0), and a pixel clock (index 1). >>> - power-domains: Should be <&mmcc MDSS_GDSC>. >>> @@ -102,6 +109,8 @@ Required properties: >>> - vddio-supply: phandle to vdd-io regulator device node >>> For 20nm PHY: >>> - vddio-supply: phandle to vdd-io regulator device node >>> +- vcca-supply: phandle to vcca regulator device node >> >> >> Did you mean to add this? > > > Yes, I didn't intend it to be a part of this patch, but this supply is > indeed needed for the > 20nm PHY. I'll move this to a separate patch. actually, this looks correct, just formatted counter-intuitively by git-format-patch.. vcca-supply for 20nm was introduced by "dt-bindings: display: msm/dsi: Fix the PHY regulator supply props", but when 14nm phy is added in this patch, it shows the addition of same line beneath 14nm PHY as an addition above the line. So I don't think it needs to be split up. BR, -R > Thanks, > Archit > > >> >>> + For 14nm PHY: >>> - vcca-supply: phandle to vcca regulator device node >>> Optional properties: >>> -- >>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora >>> Forum, >>> hosted by The Linux Foundation >>> > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 01/31/2018 09:50 PM, Rob Clark wrote: > On Wed, Jan 31, 2018 at 1:40 AM, Archit Taneja <architt@codeaurora.org> wrote: >> >> >> On 01/29/2018 10:45 PM, Rob Herring wrote: >>> >>> On Wed, Jan 17, 2018 at 03:04:47PM +0530, Archit Taneja wrote: >>>> >>>> Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096). >>>> From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required, >>>> but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names >>>> each PHY revision needs. >>>> >>>> Cc: Rob Herring <robh@kernel.org> >>>> Cc: devicetree@vger.kernel.org >>>> Signed-off-by: Archit Taneja <architt@codeaurora.org> >>>> --- >>>> Documentation/devicetree/bindings/display/msm/dsi.txt | 13 >>>> +++++++++++-- >>>> 1 file changed, 11 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt >>>> b/Documentation/devicetree/bindings/display/msm/dsi.txt >>>> index 9c3ad6bbb9f0..26a1796b7145 100644 >>>> --- a/Documentation/devicetree/bindings/display/msm/dsi.txt >>>> +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt >>>> @@ -86,12 +86,19 @@ Required properties: >>>> * "qcom,dsi-phy-28nm-lp" >>>> * "qcom,dsi-phy-20nm" >>>> * "qcom,dsi-phy-28nm-8960" >>>> -- reg: Physical base address and length of the registers of PLL, PHY and >>>> PHY >>>> - regulator >>>> + * "qcom,dsi-phy-14nm" >>>> +- reg: Physical base address and length of the registers of PLL, PHY. >>>> Some >>>> + revisions require the PHY regulator base address, whereas others >>>> require the >>>> + PHY lane base address. See below for each PHY revision. >>>> - reg-names: The names of register regions. The following regions are >>>> required: >>>> + For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: >>>> * "dsi_pll" >>>> * "dsi_phy" >>>> * "dsi_phy_regulator" >>>> + For DSI 14nm PHY: >>>> + * "dsi_pll" >>>> + * "dsi_phy" >>>> + * "dsi_phy_lane" >>>> - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, >>>> creating >>>> 2 clocks: A byte clock (index 0), and a pixel clock (index 1). >>>> - power-domains: Should be <&mmcc MDSS_GDSC>. >>>> @@ -102,6 +109,8 @@ Required properties: >>>> - vddio-supply: phandle to vdd-io regulator device node >>>> For 20nm PHY: >>>> - vddio-supply: phandle to vdd-io regulator device node >>>> +- vcca-supply: phandle to vcca regulator device node >>> >>> >>> Did you mean to add this? >> >> >> Yes, I didn't intend it to be a part of this patch, but this supply is >> indeed needed for the >> 20nm PHY. I'll move this to a separate patch. > > actually, this looks correct, just formatted counter-intuitively by > git-format-patch.. > > vcca-supply for 20nm was introduced by "dt-bindings: display: msm/dsi: > Fix the PHY regulator supply props", but when 14nm phy is added in > this patch, it shows the addition of same line beneath 14nm PHY as an > addition above the line. > > So I don't think it needs to be split up. Oh yeah, you're right. I guess this is okay as is, then. Thanks, Archit > > BR, > -R > >> Thanks, >> Archit >> >> >>> >>>> + For 14nm PHY: >>>> - vcca-supply: phandle to vcca regulator device node >>>> Optional properties: >>>> -- >>>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora >>>> Forum, >>>> hosted by The Linux Foundation >>>> >> >> -- >> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, >> a Linux Foundation Collaborative Project > -- > To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html >
On Wed, Jan 31, 2018 at 11:29 PM, Archit Taneja <architt@codeaurora.org> wrote: > > > On 01/31/2018 09:50 PM, Rob Clark wrote: >> >> On Wed, Jan 31, 2018 at 1:40 AM, Archit Taneja <architt@codeaurora.org> >> wrote: >>> >>> >>> >>> On 01/29/2018 10:45 PM, Rob Herring wrote: >>>> >>>> >>>> On Wed, Jan 17, 2018 at 03:04:47PM +0530, Archit Taneja wrote: >>>>> >>>>> >>>>> Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096). >>>>> From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not >>>>> required, >>>>> but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names >>>>> each PHY revision needs. >>>>> >>>>> Cc: Rob Herring <robh@kernel.org> >>>>> Cc: devicetree@vger.kernel.org >>>>> Signed-off-by: Archit Taneja <architt@codeaurora.org> >>>>> --- >>>>> Documentation/devicetree/bindings/display/msm/dsi.txt | 13 >>>>> +++++++++++-- >>>>> 1 file changed, 11 insertions(+), 2 deletions(-) >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt >>>>> b/Documentation/devicetree/bindings/display/msm/dsi.txt >>>>> index 9c3ad6bbb9f0..26a1796b7145 100644 >>>>> --- a/Documentation/devicetree/bindings/display/msm/dsi.txt >>>>> +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt >>>>> @@ -86,12 +86,19 @@ Required properties: >>>>> * "qcom,dsi-phy-28nm-lp" >>>>> * "qcom,dsi-phy-20nm" >>>>> * "qcom,dsi-phy-28nm-8960" >>>>> -- reg: Physical base address and length of the registers of PLL, PHY >>>>> and >>>>> PHY >>>>> - regulator >>>>> + * "qcom,dsi-phy-14nm" >>>>> +- reg: Physical base address and length of the registers of PLL, PHY. >>>>> Some >>>>> + revisions require the PHY regulator base address, whereas others >>>>> require the >>>>> + PHY lane base address. See below for each PHY revision. >>>>> - reg-names: The names of register regions. The following regions >>>>> are >>>>> required: >>>>> + For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: >>>>> * "dsi_pll" >>>>> * "dsi_phy" >>>>> * "dsi_phy_regulator" >>>>> + For DSI 14nm PHY: >>>>> + * "dsi_pll" >>>>> + * "dsi_phy" >>>>> + * "dsi_phy_lane" >>>>> - clock-cells: Must be 1. The DSI PHY block acts as a clock >>>>> provider, >>>>> creating >>>>> 2 clocks: A byte clock (index 0), and a pixel clock (index 1). >>>>> - power-domains: Should be <&mmcc MDSS_GDSC>. >>>>> @@ -102,6 +109,8 @@ Required properties: >>>>> - vddio-supply: phandle to vdd-io regulator device node >>>>> For 20nm PHY: >>>>> - vddio-supply: phandle to vdd-io regulator device node >>>>> +- vcca-supply: phandle to vcca regulator device node >>>> >>>> >>>> >>>> Did you mean to add this? >>> >>> >>> >>> Yes, I didn't intend it to be a part of this patch, but this supply is >>> indeed needed for the >>> 20nm PHY. I'll move this to a separate patch. >> >> >> actually, this looks correct, just formatted counter-intuitively by >> git-format-patch.. >> >> vcca-supply for 20nm was introduced by "dt-bindings: display: msm/dsi: >> Fix the PHY regulator supply props", but when 14nm phy is added in >> this patch, it shows the addition of same line beneath 14nm PHY as an >> addition above the line. >> >> So I don't think it needs to be split up. > > > Oh yeah, you're right. I guess this is okay as is, then. Doh! Reviewed-by: Rob Herring <robh@kernel.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 9c3ad6bbb9f0..26a1796b7145 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -86,12 +86,19 @@ Required properties: * "qcom,dsi-phy-28nm-lp" * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" -- reg: Physical base address and length of the registers of PLL, PHY and PHY - regulator + * "qcom,dsi-phy-14nm" +- reg: Physical base address and length of the registers of PLL, PHY. Some + revisions require the PHY regulator base address, whereas others require the + PHY lane base address. See below for each PHY revision. - reg-names: The names of register regions. The following regions are required: + For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: * "dsi_pll" * "dsi_phy" * "dsi_phy_regulator" + For DSI 14nm PHY: + * "dsi_pll" + * "dsi_phy" + * "dsi_phy_lane" - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating 2 clocks: A byte clock (index 0), and a pixel clock (index 1). - power-domains: Should be <&mmcc MDSS_GDSC>. @@ -102,6 +109,8 @@ Required properties: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: - vddio-supply: phandle to vdd-io regulator device node +- vcca-supply: phandle to vcca regulator device node + For 14nm PHY: - vcca-supply: phandle to vcca regulator device node Optional properties: