From patchwork Wed Jan 17 00:35:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gurchetan Singh X-Patchwork-Id: 861969 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="eouSL8fc"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zLp6l171rz9sDB for ; Wed, 17 Jan 2018 11:36:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750861AbeAQAgO (ORCPT ); Tue, 16 Jan 2018 19:36:14 -0500 Received: from mail-pg0-f67.google.com ([74.125.83.67]:33289 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750750AbeAQAgN (ORCPT ); Tue, 16 Jan 2018 19:36:13 -0500 Received: by mail-pg0-f67.google.com with SMTP id i196so10385750pgd.0 for ; Tue, 16 Jan 2018 16:36:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=P7EJLfY2Rs0Rev9kJqaWrOdN/t0deug+4l8kBLTACVU=; b=eouSL8fcwDvcsehLnHbhUc9tCzlJ8n7azhyRE+R9LOCsDi9zLuC+6pZQH6ggUNyir9 kNtb6HOdSfKpDojMcj9zCGNe3aYg/oXfn5tuaRu57C+NzQFirQhn4Luqr/NYIoOhuAMN 7iCXVwBStQ9BK/deKD9k8S/Gh56woKOYJON4Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=P7EJLfY2Rs0Rev9kJqaWrOdN/t0deug+4l8kBLTACVU=; b=RIkcc75kmxPqqRknJ4NSYZo5Z9Prq6cijEdWFXVMyZ9bLOjvzEp5LT8UEq+CnMbXX+ pGHpWtIL0BzgWVc5aGVE2asY8eDwtkPYw4afCyns/U2PcE3Z6pVOWvDQjFpsapdks69B HDKrH7enXKU+GEeJbuppeJpKQqsKeQ99updHpTYC8xg0xMLjkWSWULTD9zsEdUilc63G 7k3uPxFYEhsRPNPXBemjGQYjjPkXtoXceOwvhOD93Q9M4f8v+sWtCpob+zu0OLGHu3mp 2FjJs655Pa/9RQ+6mGAv3+GElve2b0Kw7awm9FaJG1SOxRDDEB1NUNi8dGm/mw6F7sWA RcNQ== X-Gm-Message-State: AKGB3mIQEfM2wqMmf5Dlu61vRX1qqWJZRCHqH7WYitlgNq31f00CZnlF RS8p2TAii4SqSWuKw3DRO9myJQ== X-Google-Smtp-Source: ACJfBoveFlHyTDkrlnYjmvnVw+02yaHk/rWUXBxmEJzheFjZTt7XJ/8pA9CKNMOby6XCwFNgBMKZkw== X-Received: by 10.99.184.17 with SMTP id p17mr31996045pge.357.1516149372970; Tue, 16 Jan 2018 16:36:12 -0800 (PST) Received: from gurchetansingh0.mtv.corp.google.com ([2620:0:1000:1600:1dfc:23a3:37e7:107c]) by smtp.gmail.com with ESMTPSA id 15sm5792104pfi.97.2018.01.16.16.36.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 16 Jan 2018 16:36:12 -0800 (PST) From: Gurchetan Singh To: dri-devel@lists.freedesktop.org Cc: thierry.reding@gmail.com, heiko@sntech.de, daniel.vetter@intel.com, chris@chris-wilson.co.uk, linux-tegra@vger.kernel.org, Gurchetan Singh Subject: [PATCH 2/4] drm: add additional parameter in drm_flush_pages() and drm_flush_sg() Date: Tue, 16 Jan 2018 16:35:57 -0800 Message-Id: <20180117003559.67837-2-gurchetansingh@chromium.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20180117003559.67837-1-gurchetansingh@chromium.org> References: <20180117003559.67837-1-gurchetansingh@chromium.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org We've found the DMA API is effective for flushing the cache on ARM devices, and it requires a struct device *. Signed-off-by: Gurchetan Singh --- drivers/gpu/drm/drm_cache.c | 5 +++-- drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_gem_clflush.c | 2 +- drivers/gpu/drm/ttm/ttm_tt.c | 2 +- drivers/gpu/drm/vgem/vgem_drv.c | 2 +- include/drm/drm_cache.h | 5 +++-- 6 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index 89cdd32fe1f3..3d2bb9d71a60 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -78,7 +78,8 @@ static void drm_cache_flush_clflush(struct page *pages[], * to a page in the array. */ void -drm_flush_pages(struct page *pages[], unsigned long num_pages) +drm_flush_pages(struct device *dev, struct page *pages[], + unsigned long num_pages) { #if defined(CONFIG_X86) @@ -119,7 +120,7 @@ EXPORT_SYMBOL(drm_flush_pages); * sg. */ void -drm_flush_sg(struct sg_table *st) +drm_flush_sg(struct device *dev, struct sg_table *st) { #if defined(CONFIG_X86) if (static_cpu_has(X86_FEATURE_CLFLUSH)) { diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index fe191d0e84e1..045866f2b5dd 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -259,7 +259,7 @@ __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, if (needs_clflush && (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 && !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) - drm_flush_sg(pages); + drm_flush_sg(obj->base.dev->dev, pages); __start_cpu_write(obj); } diff --git a/drivers/gpu/drm/i915/i915_gem_clflush.c b/drivers/gpu/drm/i915/i915_gem_clflush.c index f413c5e5735d..b5938f14141f 100644 --- a/drivers/gpu/drm/i915/i915_gem_clflush.c +++ b/drivers/gpu/drm/i915/i915_gem_clflush.c @@ -71,7 +71,7 @@ static const struct dma_fence_ops i915_clflush_ops = { static void __i915_do_clflush(struct drm_i915_gem_object *obj) { GEM_BUG_ON(!i915_gem_object_has_pages(obj)); - drm_flush_sg(obj->mm.pages); + drm_flush_sg(obj->base.dev->dev, obj->mm.pages); intel_fb_obj_flush(obj, ORIGIN_CPU); } diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 59e272a58752..fb2382d01bba 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -122,7 +122,7 @@ static int ttm_tt_set_caching(struct ttm_tt *ttm, } if (ttm->caching_state == tt_cached) - drm_flush_pages(ttm->pages, ttm->num_pages); + drm_flush_pages(NULL, ttm->pages, ttm->num_pages); for (i = 0; i < ttm->num_pages; ++i) { cur_page = ttm->pages[i]; diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c index 802a97e1a4bf..35bfdfb746a7 100644 --- a/drivers/gpu/drm/vgem/vgem_drv.c +++ b/drivers/gpu/drm/vgem/vgem_drv.c @@ -325,7 +325,7 @@ static int vgem_prime_pin(struct drm_gem_object *obj) /* Flush the object from the CPU cache so that importers can rely * on coherent indirect access via the exported dma-address. */ - drm_flush_pages(pages, n_pages); + drm_flush_pages(obj->dev->dev, pages, n_pages); return 0; } diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h index 25c029470315..cb77315dd8dd 100644 --- a/include/drm/drm_cache.h +++ b/include/drm/drm_cache.h @@ -35,8 +35,9 @@ #include -void drm_flush_pages(struct page *pages[], unsigned long num_pages); -void drm_flush_sg(struct sg_table *st); +void drm_flush_pages(struct device *dev, struct page *pages[], + unsigned long num_pages); +void drm_flush_sg(struct device *dev, struct sg_table *st); void drm_clflush_virt_range(void *addr, unsigned long length); static inline bool drm_arch_can_wc_memory(void)