diff mbox series

[U-Boot,3/4] ARC: HSDK: CGU: add 'Hz' when printing clock frequency

Message ID 20180116174428.21306-3-Eugeniy.Paltsev@synopsys.com
State Accepted, archived
Commit 320c8a1a860e91983955b9d69014324a1c1c0ad8
Delegated to: Alexey Brodkin
Headers show
Series [U-Boot,1/4] ARC: HSDK: CGU: update AXI, TUN, ARC clock options | expand

Commit Message

Eugeniy Paltsev Jan. 16, 2018, 5:44 p.m. UTC 
Add 'Hz' when printing clock frequency in error messages.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
---
 drivers/clk/clk-hsdk-cgu.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index 64bb1db..4362d58 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -492,7 +492,7 @@  static ulong pll_set(struct clk *sclk, ulong rate)
 		}
 	}
 
-	pr_err("invalid rate=%ld, parent_rate=%d\n", best_rate, PARENT_RATE);
+	pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate, PARENT_RATE);
 
 	return -EINVAL;
 }
@@ -623,14 +623,14 @@  static ulong idiv_set(struct clk *sclk, ulong rate)
 	}
 
 	if (div_factor & ~CGU_IDIV_MASK) {
-		pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: max divider valie is%d\n",
+		pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
 		       rate, parent_rate, div_factor, CGU_IDIV_MASK);
 
 		div_factor = CGU_IDIV_MASK;
 	}
 
 	if (div_factor == 0) {
-		pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: min divider valie is 1\n",
+		pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
 		       rate, parent_rate, div_factor);
 
 		div_factor = 1;