From patchwork Sat Jan 13 01:05:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karthikeyan Ramasubramanian X-Patchwork-Id: 860260 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="T4vf6hDM"; dkim=pass (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="IfsO5nAp"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zJLzd2L5vz9t3n for ; Sat, 13 Jan 2018 12:06:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965451AbeAMBGZ (ORCPT ); Fri, 12 Jan 2018 20:06:25 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:39008 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965304AbeAMBGW (ORCPT ); Fri, 12 Jan 2018 20:06:22 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 6A9E860C64; Sat, 13 Jan 2018 01:06:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1515805581; bh=o/NBFDJAfaz49MQ+ZucI4PHE8sutLkMaTxWkyl6gF0Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=T4vf6hDM3yTHyfts/VJfC2lDpMf2diENodm1AM7/ktpWmrgGwKeRQzC0TCL/6yob+ /FUNUO1BxgNv6TLdQ4Eewm9uUWYyYKxeuKJGtbS1v+5o+Z7wHvVi4Y9arQIyeb3DPI WoLQ+maM7zuR1rp/UBgUiI6CrPLLl9pk+XyyqvkQ= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: kramasub@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 566AA607DC; Sat, 13 Jan 2018 01:06:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1515805573; bh=o/NBFDJAfaz49MQ+ZucI4PHE8sutLkMaTxWkyl6gF0Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IfsO5nAphbSSgj54Qh3NpN+bJnK1oIAalSI2tJeR7UE0txH0XQS/e6seIi245nZsC YLV5jyz5En1Kwh+IBatu5/eYL4cNhTDJaieaSbc/Xxm3A4uMzTerwoVnIivrNHvG4z eC1HW0O29IrqVjATMLHSUq/nwPa+BRG6Ux1egV+w= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 566AA607DC Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=kramasub@codeaurora.org From: Karthikeyan Ramasubramanian To: corbet@lwn.net, andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, wsa@the-dreams.de, gregkh@linuxfoundation.org Cc: Karthikeyan Ramasubramanian , linux-doc@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, jslaby@suse.com, Sagar Dharia Subject: [PATCH v2 4/7] dt-bindings: i2c: Add device tree bindings for GENI I2C Controller Date: Fri, 12 Jan 2018 18:05:44 -0700 Message-Id: <1515805547-22816-5-git-send-email-kramasub@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1515805547-22816-1-git-send-email-kramasub@codeaurora.org> References: <1515805547-22816-1-git-send-email-kramasub@codeaurora.org> Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add device tree binding support for I2C Controller in GENI based QUP Wrapper. Signed-off-by: Sagar Dharia Signed-off-by: Karthikeyan Ramasubramanian --- .../devicetree/bindings/i2c/i2c-qcom-geni.txt | 35 ++++++++++++++++++++++ .../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 19 ++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt diff --git a/Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt b/Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt new file mode 100644 index 0000000..ea84be7 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt @@ -0,0 +1,35 @@ +Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller + +Required properties: + - compatible: Should be: + * "qcom,i2c-geni. + - reg: Should contain QUP register address and length. + - interrupts: Should contain I2C interrupt. + - clock-names: Should contain "se-clk". + - clocks: Serial engine core clock needed by the device. + - pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names + should be "active" and "sleep" for the pin confuguration when core is active + or when entering sleep state. + - #address-cells: Should be <1> Address cells for i2c device address + - #size-cells: Should be <0> as i2c addresses have no size component + +Optional property: + - clock-frequency : Desired I2C bus clock frequency in Hz. + When missing default to 400000Hz. + +Child nodes should conform to i2c bus binding. + +Example: + +i2c0: i2c@a94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_1_i2c_5_active>; + pinctrl-1 = <&qup_1_i2c_5_sleep>; + #address-cells = <1>; + #size-cells = <0>; +}; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt index 66f8a16..2ffbb3e 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt @@ -24,6 +24,9 @@ A GENI based QUP wrapper controller node can contain 0 or more child nodes representing serial devices. These serial devices can be a QCOM UART, I2C controller, spi controller, or some combination of aforementioned devices. +See the following documentation for child node definitions: +Documentation/devicetree/bindings/i2c/i2c-qcom-geni.txt + Example: qup0: qcom,geniqup0@8c0000 { compatible = "qcom,geni-se-qup"; @@ -31,4 +34,20 @@ Example: clock-names = "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + i2c0: i2c@a94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_1_i2c_5_active>; + pinctrl-1 = <&qup_1_i2c_5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + }; }