From patchwork Sat Jan 13 00:43:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 860246 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zJLYh6yjbz9t2x for ; Sat, 13 Jan 2018 11:47:36 +1100 (AEDT) Received: from localhost ([::1]:51810 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ea9yx-0006C5-3O for incoming@patchwork.ozlabs.org; Fri, 12 Jan 2018 19:47:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34339) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ea9vO-0003um-Fq for qemu-devel@nongnu.org; Fri, 12 Jan 2018 19:43:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ea9vL-0006ZU-Bk for qemu-devel@nongnu.org; Fri, 12 Jan 2018 19:43:54 -0500 Received: from mout.kundenserver.de ([217.72.192.74]:61010) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ea9vL-0006Wv-0o for qemu-devel@nongnu.org; Fri, 12 Jan 2018 19:43:51 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue103 [212.227.15.183]) with ESMTPSA (Nemesis) id 0MBr6d-1ekMXT25fr-00Aoqc; Sat, 13 Jan 2018 01:43:48 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Sat, 13 Jan 2018 01:43:34 +0100 Message-Id: <20180113004338.16867-4-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180113004338.16867-1-laurent@vivier.eu> References: <20180113004338.16867-1-laurent@vivier.eu> X-Provags-ID: V03:K0:x2mNfP8lo/ellafyb4H7WQQc13a1zCOGSCeJ7pIBUT4BunWvZYA nDUwN0NK7zqGoArRAfpGsW+4ea+ZMjFkcRRjgzTCZSMl5HjSZBF2pHmxX/S/RZQH0n2Lgg9 5PvymQHA/Bo0YcglhXNKXjeLz3QVOkwQqkZWt1coKD1FkhkCUIVOYc9d+vl8pPh4ZFXn+ci BBCB5D0RAGqjc/GVYvEJw== X-UI-Out-Filterresults: notjunk:1; V01:K0:znWoc/VQeuM=:CTfkBv/sRuuQoKzalg0XYs yN7idscmXIOZFP/DFBJWeuaIt+rw40K+fNb3JjAUWojeZEGXIgEoeCConuut58N113Vd8FmRz yokN8lj1DuQFYUXgTdh5WWIjJbWJ3QMJ5A/kJBapS7jurmzXkuBB5kxlt6GQIMIZyqZlUvQVb UV6lyhDLxu0xOk7U8sslueFyES5/ECch6XI1yPDpVC9jEIbpAL7pJMu7/MvpZFpfm3sbUihdw GUMV1yWxX8AiBJdzERenQliQwJqSQTZL1qpQnMIjnRW5WvXd8/kJ01TzarQp+ybYDRdUD5FDx Oe3uNBBo5xZgIe+2KJx9abs4r8jGDxErPupyNawqcDiUpole6M8utb89AHXJTvSVc0b6NiYPk vgFwOf/gSteP5zgs1KG6W8KEA1Jp1hmDigem1VMFG0zcf+0Ttgw+ogrHk1FyIQpfz/ykXdm1u ozUyFZk/EOyZRAtm2o3HFaoxMVAEpsS+q9801zNEy0exG6aYpsMdrwyiyxtniJ5Ams0TmWNHq aP6t1Kh1WC8TmN6QXiOVbP3ue1LAGFgXpJ9sypVmeOf8C0ZxxlC8k/VUf2aoC4tIBaKohCFia pnLbJTvhfMPnwEBu+d6izcEzAjZwr0dSwzbCQh6tBEqEzwchfgIdB666uV5k+b5nyeXB8N0mh i+ZUjSN2CgbuQW6fqpK4A7l8fT4IY9kVPmP0BS6Y/3bhIuYhRSAcID9yLR/KzuD4eEaQivgvQ g8n7W5F6i82ygo+hG9Cxu4bzpOS6bZ+pvqmFyg== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.72.192.74 Subject: [Qemu-devel] [PATCH v2 3/7] target/m68k: add Transparent Translation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Laurent Vivier Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add ittr0, ittr1, dttr0, dttr1 and manage Transparent Translations Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- target/m68k/cpu.h | 18 +++++++++++ target/m68k/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++ target/m68k/monitor.c | 4 +++ target/m68k/translate.c | 3 ++ 4 files changed, 104 insertions(+) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index b26a49e0fe..4cb75f558e 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -76,6 +76,14 @@ #define EXCP_RTE 0x100 #define EXCP_HALT_INSN 0x101 +#define M68K_DTTR0 0 +#define M68K_DTTR1 1 +#define M68K_ITTR0 2 +#define M68K_ITTR1 3 + +#define M68K_MAX_TTR 2 +#define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] + #define NB_MMU_MODES 2 #define TARGET_INSN_START_EXTRA_WORDS 1 @@ -122,6 +130,7 @@ typedef struct CPUM68KState { uint32_t urp; uint32_t srp; bool fault; + uint32_t ttr[4]; } mmu; /* Control registers. */ @@ -316,6 +325,15 @@ typedef enum { #define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2) #define M68K_INDIRECT_POINTER(addr) (addr & ~3) +/* bits for 68040 MMU Transparent Translation Registers */ +#define M68K_TTR_ADDR_BASE 0xff000000 +#define M68K_TTR_ADDR_MASK 0x00ff0000 +#define M68K_TTR_ADDR_MASK_SHIFT 8 +#define M68K_TTR_ENABLED 0x00008000 +#define M68K_TTR_SFIELD 0x00006000 +#define M68K_TTR_SFIELD_USER 0x0000 +#define M68K_TTR_SFIELD_SUPER 0x2000 + /* m68k Control Registers */ /* ColdFire */ diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 13c6bb3d25..f1d50e54b1 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -230,6 +230,19 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) case M68K_CR_ISP: env->sp[M68K_ISP] = val; return; + /* MC68040/MC68LC040 */ + case M68K_CR_ITT0: + env->mmu.ttr[M68K_ITTR0] = val; + return; + case M68K_CR_ITT1: + env->mmu.ttr[M68K_ITTR1] = val; + return; + case M68K_CR_DTT0: + env->mmu.ttr[M68K_DTTR0] = val; + return; + case M68K_CR_DTT1: + env->mmu.ttr[M68K_DTTR1] = val; + return; } cpu_abort(CPU(cpu), "Unimplemented control register write 0x%x = 0x%x\n", reg, val); @@ -260,6 +273,14 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg) /* MC68040/MC68LC040 */ case M68K_CR_URP: return env->mmu.urp; + case M68K_CR_ITT0: + return env->mmu.ttr[M68K_ITTR0]; + case M68K_CR_ITT1: + return env->mmu.ttr[M68K_ITTR1]; + case M68K_CR_DTT0: + return env->mmu.ttr[M68K_DTTR0]; + case M68K_CR_DTT1: + return env->mmu.ttr[M68K_DTTR1]; } cpu_abort(CPU(cpu), "Unimplemented control register read 0x%x\n", reg); @@ -338,6 +359,53 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, /* MMU: 68040 only */ +static int check_TTR(uint32_t ttr, int *prot, target_ulong addr, + int access_type) +{ + uint32_t base, mask; + + /* check if transparent translation is enabled */ + if ((ttr & M68K_TTR_ENABLED) == 0) { + return 0; + } + + /* check mode access */ + switch (ttr & M68K_TTR_SFIELD) { + case M68K_TTR_SFIELD_USER: + /* match only if user */ + if ((access_type & ACCESS_SUPER) != 0) { + return 0; + } + break; + case M68K_TTR_SFIELD_SUPER: + /* match only if supervisor */ + if ((access_type & ACCESS_SUPER) == 0) { + return 0; + } + break; + default: + /* all other values disable mode matching (FC2) */ + break; + } + + /* check address matching */ + + base = ttr & M68K_TTR_ADDR_BASE; + mask = (ttr & M68K_TTR_ADDR_MASK) ^ M68K_TTR_ADDR_MASK; + mask <<= M68K_TTR_ADDR_MASK_SHIFT; + + if ((addr & mask) != (base & mask)) { + return 0; + } + + *prot = PAGE_READ | PAGE_EXEC; + if ((ttr & M68K_DESC_WRITEPROT) == 0) { + *prot |= PAGE_WRITE; + } + + return 1; +} + static int get_physical_address(CPUM68KState *env, hwaddr *physical, int *prot, target_ulong address, int access_type, target_ulong *page_size) @@ -350,6 +418,17 @@ static int get_physical_address(CPUM68KState *env, hwaddr *physical, target_ulong page_mask; bool debug = access_type & ACCESS_DEBUG; int page_bits; + int i; + + /* Transparent Translation (physical = logical) */ + for (i = 0; i < M68K_MAX_TTR; i++) { + if (check_TTR(env->mmu.TTR(access_type, i), + prot, address, access_type)) { + *physical = address; + *page_size = TARGET_PAGE_SIZE; + return 0; + } + } /* Page Table Root Pointer */ *prot = PAGE_READ | PAGE_WRITE; diff --git a/target/m68k/monitor.c b/target/m68k/monitor.c index 2b83e3bc0d..a20af6b09c 100644 --- a/target/m68k/monitor.c +++ b/target/m68k/monitor.c @@ -33,6 +33,10 @@ static const MonitorDef monitor_defs[] = { { "isp", offsetof(CPUM68KState, sp[2]) }, { "urp", offsetof(CPUM68KState, mmu.urp) }, { "srp", offsetof(CPUM68KState, mmu.srp) }, + { "dttr0", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR0]) }, + { "dttr1", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR1]) }, + { "ittr0", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR0]) }, + { "ittr1", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR1]) }, { NULL }, }; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 5acee66208..af70825480 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5983,6 +5983,9 @@ void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, cpu_fprintf(f, "VBR = 0x%08x\n", env->vbr); cpu_fprintf(f, "SSW %08x TCR %08x URP %08x SRP %08x\n", env->mmu.ssw, env->mmu.tcr, env->mmu.urp, env->mmu.srp); + cpu_fprintf(f, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n", + env->mmu.ttr[M68K_DTTR0], env->mmu.ttr[M68K_DTTR1], + env->mmu.ttr[M68K_ITTR0], env->mmu.ttr[M68K_ITTR1]); #endif }