From patchwork Fri Jan 12 16:56:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 860050 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-471008-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="RQhyDXJn"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zJ86V1BQSz9t2l for ; Sat, 13 Jan 2018 03:56:49 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=j7BE38Kl73FawxY1t5p854AIUtmgO7NIt8JQQDrOW19zDo cgVWDR7fcRGOgfXDYC/osUFgrMq9r1KvIscdgbyiUZBKiZnxEIS+QUSi/TIEFp2C JeNgrTzo774makxKh0kkhVV38xF6W28XhfiRkT/9N/NEWnpfNERaho9K1HsLI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=0+tsKf/4LbzrsX4GyrqmJOU22tw=; b=RQhyDXJnsOs5ESl+ppk9 lyeugSLd4FQMg0+l13Bjwj6qJ2Bp8R5j/wcGtcVay8+QcpVFZsQPm4f/oW/xmUXV ocBQO3yvfuPEJuER7i2R1CCMW0KE5+L5ec+/jq4vTWNLH1yYaqZDFVChvAKEDJET LrKSoFkAZEeD0DmjUpOW3Hw= Received: (qmail 81390 invoked by alias); 12 Jan 2018 16:56:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 81372 invoked by uid 89); 12 Jan 2018 16:56:40 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.1 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=s4q, 256460 X-HELO: mail-io0-f176.google.com Received: from mail-io0-f176.google.com (HELO mail-io0-f176.google.com) (209.85.223.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 12 Jan 2018 16:56:39 +0000 Received: by mail-io0-f176.google.com with SMTP id i143so6519285ioa.3 for ; Fri, 12 Jan 2018 08:56:39 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=4M8boimJEZ5nXI6qRkG/zPB5t1n5Kt32xxGLWIgkaM4=; b=hUAQXqmtz6EP2FS/ckHyVTOyJgerK0jpiI8bZaH2FpGzpvADzazJaTJUBf8f82hfTj 30wNbnbmE2N/jXzfqXCXnJPt838rdS/uB41RJxndmuZPOTl0YhFVVh2ehBRrQm3tFckM nOoGGDMxT9tSpExvohbE0WzrWXt3fQBKFGud+BtHng0BspDgCLl4wkn+EcjpSmbyA6kb 4DVbeXup1Frt/IyqcxAAAnwOvux+W6/a/1pX0eUWpChKeqo9uQdq1IcVhPpsGw3b7R1m GF8Z9P1dzjR2wE0YuiMCfm9zC8yhwXWBRUXG1yHn7pyaMubfsSbcNZyYCL2AmUXhKL8l vxHw== X-Gm-Message-State: AKwxytcBOQhUn1r0PjZqqFyXRgLwo+BhFCqV0ABtwcLnsjnZ2+Vzm5HU Gp2c3fg9WX/4uusDOIrrNTORsXr/s5Je8d5VkQbIcw== X-Google-Smtp-Source: ACJfBosvsMJW8t07cbTDv2+4A9QRD5i+3l45HGqbx/Jty7sKwFVD2J1H3/etpOWpS7Nypr1H02juIdb9gHQmrU6fkO8= X-Received: by 10.107.114.4 with SMTP id n4mr25187813ioc.134.1515776197415; Fri, 12 Jan 2018 08:56:37 -0800 (PST) MIME-Version: 1.0 Received: by 10.2.130.66 with HTTP; Fri, 12 Jan 2018 08:56:36 -0800 (PST) From: Uros Bizjak Date: Fri, 12 Jan 2018 17:56:36 +0100 Message-ID: Subject: [PATCH, alpha]: Work around PR83628, performance regression when accessing arrays on alpha To: "gcc-patches@gcc.gnu.org" Hello! It turns out that without ashlsi3 named pattern combine pass won't simplify subregs in: (set (reg:SI 74) (plus:SI (subreg:SI (ashift:DI (reg:DI 17 $17 [ b ]) (const_int 2 [0x2])) 0) (reg:SI 16 $16 [ a ]))) Attached patch adds relevant insn-and-split patterns to work around this limitation. 2018-01-12 Uros Bizjak PR target/83628 * config/alpha/alpha.md (*saddsi_1): New insn_ans_split pattern. (*saddl_se_1): Ditto. (*ssubsi_1): Ditto. (*ssubl_se_1): Ditto. testsuite/ChangeLog: 2018-01-12 Uros Bizjak PR target/83628 * gcc.target/alpha/pr83628-3.c: New test. Bootstrapped and regression tested on alphaev68-linux-gnu. Committed to mainline SVN. Uros. Index: config/alpha/alpha.md =================================================================== --- config/alpha/alpha.md (revision 256460) +++ config/alpha/alpha.md (working copy) @@ -527,17 +527,50 @@ s%P2add %1,%3,%0 s%P2sub %1,%n3,%0") +(define_insn_and_split "*saddsi_1" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (plus:SI + (subreg:SI + (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r") + (match_operand:DI 2 "const23_operand" "I,I")) 0) + (match_operand:SI 3 "sext_add_operand" "rI,O")))] + "" + "#" + "" + [(set (match_dup 0) + (plus:SI (ashift:SI (match_dup 1) (match_dup 2)) + (match_dup 3)))] + "operands[1] = gen_lowpart (SImode, operands[1]);") + (define_insn "*saddl_se" [(set (match_operand:DI 0 "register_operand" "=r,r") (sign_extend:DI - (plus:SI (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r") - (match_operand:SI 2 "const23_operand" "I,I")) - (match_operand:SI 3 "sext_add_operand" "rI,O"))))] + (plus:SI + (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r") + (match_operand:SI 2 "const23_operand" "I,I")) + (match_operand:SI 3 "sext_add_operand" "rI,O"))))] "" "@ s%P2addl %1,%3,%0 s%P2subl %1,%n3,%0") +(define_insn_and_split "*saddl_se_1" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (sign_extend:DI + (plus:SI + (subreg:SI + (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r") + (match_operand:DI 2 "const23_operand" "I,I")) 0) + (match_operand:SI 3 "sext_add_operand" "rI,O"))))] + "" + "#" + "" + [(set (match_dup 0) + (sign_extend:DI + (plus:SI (ashift:SI (match_dup 1) (match_dup 2)) + (match_dup 3))))] + "operands[1] = gen_lowpart (SImode, operands[1]);") + (define_split [(set (match_operand:DI 0 "register_operand") (sign_extend:DI @@ -627,15 +660,48 @@ "" "s%P2sub %1,%3,%0") +(define_insn_and_split "*ssubsi_1" + [(set (match_operand:SI 0 "register_operand" "=r") + (minus:SI + (subreg:SI + (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r") + (match_operand:DI 2 "const23_operand" "I")) 0) + (match_operand:SI 3 "reg_or_8bit_operand" "rI")))] + "" + "#" + "" + [(set (match_dup 0) + (minus:SI (ashift:SI (match_dup 1) (match_dup 2)) + (match_dup 3)))] + "operands[1] = gen_lowpart (SImode, operands[1]);") + (define_insn "*ssubl_se" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI - (minus:SI (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r") - (match_operand:SI 2 "const23_operand" "I")) - (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))] + (minus:SI + (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r") + (match_operand:SI 2 "const23_operand" "I")) + (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))] "" "s%P2subl %1,%3,%0") +(define_insn_and_split "*ssubl_se_1" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (minus:SI + (subreg:SI + (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r") + (match_operand:DI 2 "const23_operand" "I")) 0) + (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))] + "" + "#" + "" + [(set (match_dup 0) + (sign_extend:DI + (minus:SI (ashift:SI (match_dup 1) (match_dup 2)) + (match_dup 3))))] + "operands[1] = gen_lowpart (SImode, operands[1]);") + (define_insn "subv3" [(set (match_operand:I48MODE 0 "register_operand" "=r") (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ") @@ -1200,7 +1266,7 @@ (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") (match_operand:DI 2 "const_int_operand" "P")) 0)))] - "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3" + "IN_RANGE (INTVAL (operands[2]), 1, 3)" { if (operands[2] == const1_rtx) return "addl %r1,%r1,%0"; Index: testsuite/gcc.target/alpha/pr83628-3.c =================================================================== --- testsuite/gcc.target/alpha/pr83628-3.c (nonexistent) +++ testsuite/gcc.target/alpha/pr83628-3.c (working copy) @@ -0,0 +1,29 @@ +/* PR target/83628 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +s4l (int a, int b) +{ + return a * 4 - b; +} + +int +s8l (int a, int b) +{ + return a * 8 - b; +} + +long +s4q (long a, long b) +{ + return a * 4 - b; +} + +long +s8q (long a, long b) +{ + return a * 8 - b; +} + +/* { dg-final { scan-assembler-not "\[ \t\]sub\[ql\]" } } */