From patchwork Fri Jan 12 10:08:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Wu X-Patchwork-Id: 859717 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHzB84SYcz9s7M for ; Fri, 12 Jan 2018 21:14:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933254AbeALKOM (ORCPT ); Fri, 12 Jan 2018 05:14:12 -0500 Received: from regular1.263xmail.com ([211.150.99.138]:54287 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932583AbeALKOK (ORCPT ); Fri, 12 Jan 2018 05:14:10 -0500 X-Greylist: delayed 332 seconds by postgrey-1.27 at vger.kernel.org; Fri, 12 Jan 2018 05:14:09 EST Received: from william.wu?rock-chips.com (unknown [192.168.167.153]) by regular1.263xmail.com (Postfix) with ESMTP id 335017A22; Fri, 12 Jan 2018 18:08:30 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 0A2BC3B5; Fri, 12 Jan 2018 18:08:28 +0800 (CST) X-RL-SENDER: william.wu@rock-chips.com X-FST-TO: kishon@ti.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: william.wu@rock-chips.com X-UNIQUE-TAG: <8764ee141e58f9ae9df106383ce9b509> X-ATTACHMENT-NUM: 0 X-SENDER: wulf@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 259242TX15N; Fri, 12 Jan 2018 18:08:30 +0800 (CST) From: William Wu To: kishon@ti.com Cc: robh+dt@kernel.org, heiko@sntech.de, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, frank.wang@rock-chips.com, huangtao@rock-chips.com, dianders@google.com, briannorris@google.com, groeck@google.com, daniel.meng@rock-chips.com, John.Youn@synopsys.com, william.wu@rock-chips.com, lin.huang@rock-chips.com Subject: [PATCH 1/3] dt-bindings: phy: phy-rockchip-typec: add usb3 otg reset Date: Fri, 12 Jan 2018 18:08:22 +0800 Message-Id: <1515751704-13213-2-git-send-email-william.wu@rock-chips.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1515751704-13213-1-git-send-email-william.wu@rock-chips.com> References: <1515751704-13213-1-git-send-email-william.wu@rock-chips.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds USB3 OTG reset property for rk3399 Type-C PHY to hold the USB3 controller in reset state. Signed-off-by: William Wu Tested-by: Enric Balletbo i Serra --- Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt index 6ea867e..db2902e 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt @@ -13,7 +13,7 @@ Required properties: - assigned-clock-rates : the phy core clk frequency, shall be: 50000000 - resets : a list of phandle + reset specifier pairs - reset-names : string reset name, must be: - "uphy", "uphy-pipe", "uphy-tcphy" + "uphy", "uphy-pipe", "uphy-tcphy", "usb3-otg" - extcon : extcon specifier for the Power Delivery Note, there are 2 type-c phys for RK3399, and they are almost identical, except @@ -56,8 +56,9 @@ Example: assigned-clock-rates = <50000000>; resets = <&cru SRST_UPHY0>, <&cru SRST_UPHY0_PIPE_L00>, - <&cru SRST_P_UPHY0_TCPHY>; - reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + <&cru SRST_P_UPHY0_TCPHY>, + <&cru SRST_A_USB3_OTG0>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy", "usb3-otg"; rockchip,typec-conn-dir = <0xe580 0 16>; rockchip,usb3tousb2-en = <0xe580 3 19>; rockchip,external-psm = <0xe588 14 30>; @@ -84,8 +85,9 @@ Example: assigned-clock-rates = <50000000>; resets = <&cru SRST_UPHY1>, <&cru SRST_UPHY1_PIPE_L00>, - <&cru SRST_P_UPHY1_TCPHY>; - reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + <&cru SRST_P_UPHY1_TCPHY>, + <&cru SRST_A_USB3_OTG1>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy", "usb3-otg"; rockchip,typec-conn-dir = <0xe58c 0 16>; rockchip,usb3tousb2-en = <0xe58c 3 19>; rockchip,external-psm = <0xe594 14 30>;