From patchwork Fri Jan 12 01:27:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 859441 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="LbXA2Zpm"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zHlXr3nnMz9sNr for ; Fri, 12 Jan 2018 12:29:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932446AbeALB3q (ORCPT ); Thu, 11 Jan 2018 20:29:46 -0500 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:57499 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932388AbeALB2c (ORCPT ); Thu, 11 Jan 2018 20:28:32 -0500 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id D3B768448A; Fri, 12 Jan 2018 14:28:30 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail; t=1515720510; bh=wDv1PGInGjdxIrnzmPPBSrke+zmif6MUPzynAx6MBho=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=LbXA2Zpm45nI3tQZt5jp+DsVcce5KeenjmoLJuJyj2atA2DmQA1ErmelGPhzgLf9g fJQWbOwOgmxpF/Svk3dFTCadBBhwM0tsrjy1Teq6/ksg0lyAwmuQKLIizhTHYGtfkN RqjH4c71tpVcdEqc+dQeaCeNr9Y+/p4fKCx6TWMg= Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 12 Jan 2018 14:28:30 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by smtp (Postfix) with ESMTP id 767A513EC5D; Fri, 12 Jan 2018 14:28:36 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id AD6921E1128; Fri, 12 Jan 2018 14:28:30 +1300 (NZDT) From: Chris Packham To: linux@armlinux.org.uk, bp@alien8.de, jlu@pengutronix.de Cc: Chris.Packham@alliedtelesis.co.nz, thomas.petazzoni@free-electrons.com, kernel@pengutronix.de, gregory.clement@free-electrons.com, Chris Packham , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 5/8] ARM: l2x0: add marvell, ecc-enable property for aurora Date: Fri, 12 Jan 2018 14:27:52 +1300 Message-Id: <20180112012755.20495-6-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180112012755.20495-1-chris.packham@alliedtelesis.co.nz> References: <20180112012755.20495-1-chris.packham@alliedtelesis.co.nz> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The aurora cache on the Marvell Armada-XP SoC supports ECC protection for the L2 data arrays. Add a "marvell,ecc-enable" device tree property which can be used to enable this. Signed-off-by: Chris Packham [jlu@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN] Signed-off-by: Jan Luebbe Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++ arch/arm/mm/cache-l2x0.c | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt index fbe6cb21f4cf..15a84f0ba9f1 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt @@ -76,6 +76,8 @@ Optional properties: specified to indicate that such transforms are precluded. - arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310). - arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310). +- marvell,ecc-enable : enable ECC protection on the L2 cache +- marvell,ecc-disable : disable ECC protection on the L2 cache - arm,outer-sync-disable : disable the outer sync operation on the L2 cache. Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that will randomly hang unless outer sync operations are disabled. diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index b70bee74750d..644f786e4fa9 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1505,6 +1505,13 @@ static void __init aurora_of_parse(const struct device_node *np, mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK; } + if (of_property_read_bool(np, "marvell,ecc-enable")) { + mask |= AURORA_ACR_ECC_EN; + val |= AURORA_ACR_ECC_EN; + } else if (of_property_read_bool(np, "marvell,ecc-disable")) { + mask |= AURORA_ACR_ECC_EN; + } + if (of_property_read_bool(np, "arm,parity-enable")) { mask |= AURORA_ACR_PARITY_EN; val |= AURORA_ACR_PARITY_EN;