[PR83695] Fix ICE by resetting cached scev info after interchange.

Message ID DB5PR0801MB2742078DDAB430C77EB39C67E7160@DB5PR0801MB2742.eurprd08.prod.outlook.com
State New
Headers show
Series
  • [PR83695] Fix ICE by resetting cached scev info after interchange.
Related show

Commit Message

Bin Cheng Jan. 11, 2018, 12:49 p.m.
Hi,
As explained in comment of PR83695, outdated cached scev info could be referred
by later interchange of outer loops in nest.  This simple patch fixes ICE by
resetting cached scev info after interchange.  It's expensive resetting all scev
information but might not be a problem here given we only interchange in limited
cases.

Bootstrap and test on x86_64 and AArch64.  Is it OK?

Thanks,
bin

2018-01-11  Bin Cheng  <bin.cheng@arm.com>

	PR tree-optimization/83695
	* gimple-loop-linterchange.cc
	(tree_loop_interchange::interchange_loops): Call scev_reset_htab to
	reset cached scev information after interchange.
	(pass_linterchange::execute): Remove call to scev_reset_htab.

gcc/testsuite
2018-01-11  Bin Cheng  <bin.cheng@arm.com>

	PR tree-optimization/83695
	* gcc.dg/tree-ssa/pr83695.c: New test.

Comments

Richard Biener Jan. 11, 2018, 1:41 p.m. | #1
On Thu, Jan 11, 2018 at 1:49 PM, Bin Cheng <Bin.Cheng@arm.com> wrote:
> Hi,
> As explained in comment of PR83695, outdated cached scev info could be referred
> by later interchange of outer loops in nest.  This simple patch fixes ICE by
> resetting cached scev info after interchange.  It's expensive resetting all scev
> information but might not be a problem here given we only interchange in limited
> cases.
>
> Bootstrap and test on x86_64 and AArch64.  Is it OK?

Ok.

Richard.

> Thanks,
> bin
>
> 2018-01-11  Bin Cheng  <bin.cheng@arm.com>
>
>         PR tree-optimization/83695
>         * gimple-loop-linterchange.cc
>         (tree_loop_interchange::interchange_loops): Call scev_reset_htab to
>         reset cached scev information after interchange.
>         (pass_linterchange::execute): Remove call to scev_reset_htab.
>
> gcc/testsuite
> 2018-01-11  Bin Cheng  <bin.cheng@arm.com>
>
>         PR tree-optimization/83695
>         * gcc.dg/tree-ssa/pr83695.c: New test.

Patch

diff --git a/gcc/gimple-loop-interchange.cc b/gcc/gimple-loop-interchange.cc
index 01a26c0..eb35263 100644
--- a/gcc/gimple-loop-interchange.cc
+++ b/gcc/gimple-loop-interchange.cc
@@ -1119,6 +1119,10 @@  tree_loop_interchange::interchange_loops (loop_cand &iloop, loop_cand &oloop)
   oloop.m_loop->any_likely_upper_bound = false;
   free_numbers_of_iterations_estimates (oloop.m_loop);
 
+  /* Clear all cached scev information.  This is expensive but shouldn't be
+     a problem given we interchange in very limited times.  */
+  scev_reset_htab ();
+
   /* ???  The association between the loop data structure and the
      CFG changed, so what was loop N at the source level is now
      loop M.  We should think of retaining the association or breaking
@@ -2070,9 +2074,6 @@  pass_linterchange::execute (function *fun)
       loop_nest.release ();
     }
 
-  if (changed_p)
-    scev_reset_htab ();
-
   return changed_p ? (TODO_update_ssa_only_virtuals) : 0;
 }
 
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr83695.c b/gcc/testsuite/gcc.dg/tree-ssa/pr83695.c
new file mode 100644
index 0000000..af56a31
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr83695.c
@@ -0,0 +1,23 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+int a[3][3][3], b, d;
+short c;
+unsigned char e;
+
+static void f ()
+{
+  for (c = 0; c < 2; c++)
+      for (e = 0; e < 3; e++)
+        for (b = 0; b < 3; b++)
+          a[b][e][b] = 0;
+  while (1)
+    ;
+}
+
+int main ()
+{
+  if (d)
+    f ();
+  return 0;
+}