[v2,02/21] RISC-V ELF Machine Definition

Message ID	1515628000-93285-3-git-send-email-mjc@sifive.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Michael Clark <mjc@sifive.com> To: qemu-devel@nongnu.org Date: Wed, 10 Jan 2018 15:46:21 -0800 Message-Id: <1515628000-93285-3-git-send-email-mjc@sifive.com> In-Reply-To: <1515628000-93285-1-git-send-email-mjc@sifive.com> References: <1515628000-93285-1-git-send-email-mjc@sifive.com> Subject: [Qemu-devel] [PATCH v2 02/21] RISC-V ELF Machine Definition Precedence: list Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, RISC-V Patches <patches+subscribe@groups.riscv.org>, Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>, Sagar Karandikar <sagark@eecs.berkeley.edu> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	RISC-V QEMU Port Submission v2 \| expand [v2,00/21] RISC-V QEMU Port Submission v2 [v2,01/21] RISC-V Maintainers [v2,02/21] RISC-V ELF Machine Definition [v2,03/21] RISC-V CPU Core Definition [v2,04/21] RISC-V Disassembler [v2,05/21] RISC-V CPU Helpers [v2,06/21] RISC-V FPU Support [v2,07/21] RISC-V GDB Stub [v2,08/21] RISC-V TCG Code Generation [v2,09/21] RISC-V Physical Memory Protection [v2,10/21] RISC-V Linux User Emulation [v2,11/21] RISC-V HTIF Console [v2,12/21] RISC-V HART Array [v2,13/21] SiFive RISC-V CLINT Block [v2,14/21] SiFive RISC-V PLIC Block [v2,15/21] RISC-V Spike Machines [v2,16/21] RISC-V VirtIO Machine [v2,17/21] SiFive RISC-V UART Device [v2,18/21] SiFive RISC-V PRCI Block [v2,19/21] SiFive Freedom E300 RISC-V Machine [v2,20/21] SiFive Freedom U500 RISC-V Machine [v2,21/21] RISC-V Build Infrastructure

Message ID

1515628000-93285-3-git-send-email-mjc@sifive.com

State

New

Headers

From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Date: Wed, 10 Jan 2018 15:46:21 -0800
Message-Id: <1515628000-93285-3-git-send-email-mjc@sifive.com>
In-Reply-To: <1515628000-93285-1-git-send-email-mjc@sifive.com>
References: <1515628000-93285-1-git-send-email-mjc@sifive.com>
Subject: [Qemu-devel] [PATCH v2 02/21] RISC-V ELF Machine Definition
Precedence: list
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	RISC-V Patches <patches+subscribe@groups.riscv.org>,
	Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

RISC-V QEMU Port Submission v2 | expand

Commit Message

Michael Clark Jan. 10, 2018, 11:46 p.m. UTC

Define RISC-V ELF machine EM_RISCV 243

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
---
 include/elf.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/elf.h b/include/elf.h
index e8a515c..8e457fc 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -112,6 +112,8 @@  typedef int64_t  Elf64_Sxword;
 
 #define EM_UNICORE32    110     /* UniCore32 */
 
+#define EM_RISCV        243     /* RISC-V */
+
 /*
  * This is an interim value that we will use until the committee comes
  * up with a final number.