From patchwork Wed Jan 10 14:47:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philippe Bergheaud X-Patchwork-Id: 858325 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zGsM70cKDz9s74 for ; Thu, 11 Jan 2018 01:48:19 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zGsM66MB0zF0kZ for ; Thu, 11 Jan 2018 01:48:18 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=felix@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zGsLq44H5zF0gg for ; Thu, 11 Jan 2018 01:48:03 +1100 (AEDT) Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w0AEjORd052997 for ; Wed, 10 Jan 2018 09:48:00 -0500 Received: from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110]) by mx0b-001b2d01.pphosted.com with ESMTP id 2fdhbck4pu-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 10 Jan 2018 09:47:59 -0500 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 10 Jan 2018 14:47:55 -0000 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w0AEltIu64880700; Wed, 10 Jan 2018 14:47:55 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D2C2F42049; Wed, 10 Jan 2018 14:41:30 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B707C4203F; Wed, 10 Jan 2018 14:41:30 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 10 Jan 2018 14:41:30 +0000 (GMT) Received: from w541.lab.toulouse-stg.fr.ibm.com (t42p.lab.toulouse-stg.fr.ibm.com [9.101.4.37]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id A7E07220164; Wed, 10 Jan 2018 15:47:54 +0100 (CET) From: Philippe Bergheaud To: skiboot@lists.ozlabs.org Date: Wed, 10 Jan 2018 15:47:36 +0100 X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180110144736.18711-1-felix@linux.vnet.ibm.com> References: <20180110144736.18711-1-felix@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18011014-0016-0000-0000-000005163501 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18011014-0017-0000-0000-0000285293F9 Message-Id: <20180110144736.18711-2-felix@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-10_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801100207 Subject: [Skiboot] [PATCH v4 2/2] phb4: set PBCQ Tunnel BAR for tunneled operations X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: benh@au1.ibm.com MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" P9 supports PCI tunneled operations (atomics and as_notify) that are initiated by devices. A subset of the tunneled operations require a response, that must be sent back from the host to the device. For example, an atomic compare and swap will return the compare status, as swap will only performed in case of success. Similarly, as_notify reports if the target thread has been woken up or not, because the operation may fail. To enable tunneled operations, a device driver must tell the host where it expects tunneled operation responses, by setting the PBCQ Tunnel BAR Response register with a specific value within the range of its BARs. This register is currently initialized by enable_capi_mode(). But, as tunneled operations may also operate in PCI mode, a new API is required to set the PBCQ Tunnel BAR Response register, without switching to CAPI mode. This patch provides two new OPAL calls to get/set the PBCQ Tunnel BAR Response register. Note: as there is only one PBCQ Tunnel BAR register, shared between all the devices connected to the same PHB, only one of these devices will be able to use tunneled operations, at any time. Signed-off-by: Philippe Bergheaud Reviewed-by: Frederic Barrat Reviewed-by: Christophe Lombard clombard@linux.vnet.ibm.com --- Changelog: v2: Adjust new OPAL call numbers. v3: Rebase on skiboot 5.9.6. Document new OPAL calls in doc/opal-api. v4: opal_pci_get_pbcq_tunnel_bar(): - check that addr parameter is valid - update doc/opal-api enable_capi_mode(): - explain why we do not touch an existing tunnel bar value - reuse psl tnr addr value verbatim, and shift it by 8 --- core/pci-opal.c | 36 ++++++++++ .../opal-pci-get-set-pbcq-tunnel-bar-159-160.rst | 76 ++++++++++++++++++++++ hw/phb4.c | 71 ++++++++++++++++++-- include/opal-api.h | 4 +- include/pci.h | 4 ++ 5 files changed, 185 insertions(+), 6 deletions(-) create mode 100644 doc/opal-api/opal-pci-get-set-pbcq-tunnel-bar-159-160.rst diff --git a/core/pci-opal.c b/core/pci-opal.c index b8aec941..77e965cc 100644 --- a/core/pci-opal.c +++ b/core/pci-opal.c @@ -1016,3 +1016,39 @@ static int64_t opal_pci_set_p2p(uint64_t phbid_init, uint64_t phbid_target, return OPAL_SUCCESS; } opal_call(OPAL_PCI_SET_P2P, opal_pci_set_p2p, 4); + +static int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr) +{ + struct phb *phb = pci_get_phb(phb_id); + + if (!opal_addr_valid(addr)) + return OPAL_PARAMETER; + + if (!phb) + return OPAL_PARAMETER; + if (!phb->ops->get_tunnel_bar) + return OPAL_UNSUPPORTED; + + phb_lock(phb); + phb->ops->get_tunnel_bar(phb, addr); + phb_unlock(phb); + return OPAL_SUCCESS; +} +opal_call(OPAL_PCI_GET_PBCQ_TUNNEL_BAR, opal_pci_get_pbcq_tunnel_bar, 2); + +static int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr) +{ + struct phb *phb = pci_get_phb(phb_id); + int64_t rc; + + if (!phb) + return OPAL_PARAMETER; + if (!phb->ops->set_tunnel_bar) + return OPAL_UNSUPPORTED; + + phb_lock(phb); + rc = phb->ops->set_tunnel_bar(phb, addr); + phb_unlock(phb); + return rc; +} +opal_call(OPAL_PCI_SET_PBCQ_TUNNEL_BAR, opal_pci_set_pbcq_tunnel_bar, 2); diff --git a/doc/opal-api/opal-pci-get-set-pbcq-tunnel-bar-159-160.rst b/doc/opal-api/opal-pci-get-set-pbcq-tunnel-bar-159-160.rst new file mode 100644 index 00000000..6e99d8ac --- /dev/null +++ b/doc/opal-api/opal-pci-get-set-pbcq-tunnel-bar-159-160.rst @@ -0,0 +1,76 @@ +OPAL_PCI_GET_PBCQ_TUNNEL_BAR +============================ +:: + + #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 160 + + int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr) + +The host calls this function to read the address out of the PBCQ Tunnel +Bar register. + +Parameters +---------- +:: + + uint64_t phb_id + uint64_t *addr + +``phb_id`` + The value from the PHB node ibm,opal-phbid property for the device. + +``addr`` + A pointer to where the address stored in the PBCQ Tunnel Bar register + will be copied. + +Return Values +------------- + +``OPAL_SUCCESS`` + Operation was successful + +``OPAL_PARAMETER`` + Invalid PHB or addr parameter + +``OPAL_UNSUPPORTED`` + Not supported by hardware + +OPAL_PCI_SET_PBCQ_TUNNEL_BAR +============================ +:: + + #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 161 + + int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr) + +The host calls this function to set the PBCQ Tunnel Bar register. + +Parameters +---------- +:: + + uint64_t phb_id + uint64_t addr + +``phb_id`` + The value from the PHB node ibm,opal-phbid property for the device. + +``addr`` + The value of the address chosen for the PBCQ Tunnel Bar register. + If the address is 0, then the PBCQ Tunnel Bar register will be reset. + It the address is non-zero, then the PBCQ Tunnel Bar register will be + set with :: + + Bit[0:42] Bit[8:50] of the address + +Return Values +------------- + +``OPAL_SUCCESS`` + Operation was successful + +``OPAL_PARAMETER`` + Invalid PHB or addr parameter + +``OPAL_UNSUPPORTED`` + Not supported by hardware diff --git a/hw/phb4.c b/hw/phb4.c index bbeca73b..86683691 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3799,12 +3799,24 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number, ((u64)CAPIMASK << 32) | PHB_CAPI_CMPM_ENABLE); if (!(p->rev == PHB4_REV_NIMBUS_DD10)) { - /* PBCQ Tunnel Bar Register - * Write Tunnel register to match PSL TNR register + /* + * PBCQ Tunnel Bar Register + * + * If set, for example by a driver that may already have + * tweaked the tunnel bar, then we do not touch it when + * entering capi mode. It's up to the driver to handle it. + * + * If unset, then we use the PSL_TNR_ADDR[TNR_Addr] reset + * value. For fpga/cxl, this code will define the tunnel bar. */ - xscom_write(p->chip_id, - p->pe_stk_xscom + XPEC_NEST_STK_TUNNEL_BAR, - 0x020000E000000000); + xscom_read(p->chip_id, + p->pe_stk_xscom + XPEC_NEST_STK_TUNNEL_BAR, ®); + if (!reg) { + reg = 0x00020000E0000000ull << 8; + xscom_write(p->chip_id, + p->pe_stk_xscom + XPEC_NEST_STK_TUNNEL_BAR, + reg); + } /* PB AIB Hardware Control Register * Wait 32 PCI clocks for a credit to become available @@ -4051,6 +4063,53 @@ static int64_t phb4_set_capp_recovery(struct phb *phb) return 0; } +/* + * Return the address out of a PBCQ Tunnel Bar register. + */ +static void phb4_get_tunnel_bar(struct phb *phb, uint64_t *addr) +{ + struct phb4 *p = phb_to_phb4(phb); + uint64_t val; + + xscom_read(p->chip_id, p->pe_stk_xscom + XPEC_NEST_STK_TUNNEL_BAR, + &val); + *addr = val >> 8; +} + +/* + * Set PBCQ Tunnel Bar register. + * Store addr bits [8:50] in PBCQ Tunnel Bar register bits [0:42]. + * Note that addr bits [8:50] must also match PSL_TNR_ADDR[8:50]. + * Reset register if val == 0. + * + * This interface is required to let device drivers set the Tunnel Bar + * value of their choice. + * + * Compatibility with older versions of linux, that do not set the + * Tunnel Bar with phb4_set_tunnel_bar(), is ensured by enable_capi_mode(), + * that will set the default value that used to be assumed. + */ +static int64_t phb4_set_tunnel_bar(struct phb *phb, uint64_t addr) +{ + struct phb4 *p = phb_to_phb4(phb); + uint64_t mask = 0x00FFFFFFFFFFE000ULL; + + if (!addr) { + /* Reset register */ + xscom_write(p->chip_id, + p->pe_stk_xscom + XPEC_NEST_STK_TUNNEL_BAR, addr); + return OPAL_SUCCESS; + } + if ((addr & ~mask)) + return OPAL_PARAMETER; + if (!(addr & mask)) + return OPAL_PARAMETER; + + xscom_write(p->chip_id, p->pe_stk_xscom + XPEC_NEST_STK_TUNNEL_BAR, + (addr & mask) << 8); + return OPAL_SUCCESS; +} + static const struct phb_ops phb4_ops = { .cfg_read8 = phb4_pcicfg_read8, .cfg_read16 = phb4_pcicfg_read16, @@ -4086,6 +4145,8 @@ static const struct phb_ops phb4_ops = { .set_capi_mode = phb4_set_capi_mode, .set_p2p = phb4_set_p2p, .set_capp_recovery = phb4_set_capp_recovery, + .get_tunnel_bar = phb4_get_tunnel_bar, + .set_tunnel_bar = phb4_set_tunnel_bar, }; static void phb4_init_ioda3(struct phb4 *p) diff --git a/include/opal-api.h b/include/opal-api.h index f0ed5f6c..ac877046 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -215,7 +215,9 @@ #define OPAL_SENSOR_GROUP_CLEAR 156 #define OPAL_PCI_SET_P2P 157 #define OPAL_QUIESCE 158 -#define OPAL_LAST 158 +#define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 159 +#define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 160 +#define OPAL_LAST 160 #define QUIESCE_HOLD 1 /* Spin all calls at entry */ #define QUIESCE_REJECT 2 /* Fail all calls with OPAL_BUSY */ diff --git a/include/pci.h b/include/pci.h index c085b6b8..97c8dfe4 100644 --- a/include/pci.h +++ b/include/pci.h @@ -333,6 +333,10 @@ struct phb_ops { /* PCI peer-to-peer setup */ void (*set_p2p)(struct phb *phb, uint64_t mode, uint64_t flags, uint16_t pe_number); + + /* Get/set PBCQ Tunnel BAR register */ + void (*get_tunnel_bar)(struct phb *phb, uint64_t *addr); + int64_t (*set_tunnel_bar)(struct phb *phb, uint64_t addr); }; enum phb_type {