From patchwork Mon Mar 7 22:32:41 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 85829 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CFC7DB6EEC for ; Tue, 8 Mar 2011 09:45:17 +1100 (EST) Received: from localhost ([127.0.0.1]:45973 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pwj4v-0001Gr-QC for incoming@patchwork.ozlabs.org; Mon, 07 Mar 2011 17:39:01 -0500 Received: from [140.186.70.92] (port=55187 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PwizC-0006rI-C0 for qemu-devel@nongnu.org; Mon, 07 Mar 2011 17:33:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pwiz9-0003qr-N3 for qemu-devel@nongnu.org; Mon, 07 Mar 2011 17:33:06 -0500 Received: from mail.serverraum.org ([78.47.150.89]:38941) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pwiz9-0003pQ-CF for qemu-devel@nongnu.org; Mon, 07 Mar 2011 17:33:03 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.serverraum.org (Postfix) with ESMTP id 167063EF13; Mon, 7 Mar 2011 23:33:03 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at mail.serverraum.org Received: from mail.serverraum.org ([127.0.0.1]) by localhost (web.serverraum.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4UXycwnFggPh; Mon, 7 Mar 2011 23:33:02 +0100 (CET) Received: from thanatos.fritz.box (91-67-5-72-dynip.superkabel.de [91.67.5.72]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.serverraum.org (Postfix) with ESMTPSA id B9A513EEFA; Mon, 7 Mar 2011 23:33:02 +0100 (CET) From: Michael Walle To: qemu-devel@nongnu.org Date: Mon, 7 Mar 2011 23:32:41 +0100 Message-Id: <1299537165-16711-11-git-send-email-michael@walle.cc> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299537165-16711-1-git-send-email-michael@walle.cc> References: <1299537165-16711-1-git-send-email-michael@walle.cc> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 78.47.150.89 Cc: "Edgar E. Iglesias" , Michael Walle , Alexander Graf Subject: [Qemu-devel] [PATCH 10/14] lm32: add Milkymist UART support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds support for Milkymist's simple UART. Signed-off-by: Michael Walle --- Makefile.target | 1 + hw/milkymist-uart.c | 180 +++++++++++++++++++++++++++++++++++++++++++++++++++ trace-events | 6 ++ 3 files changed, 187 insertions(+), 0 deletions(-) create mode 100644 hw/milkymist-uart.c diff --git a/Makefile.target b/Makefile.target index 0aae6d0..c78e9d4 100644 --- a/Makefile.target +++ b/Makefile.target @@ -264,6 +264,7 @@ obj-lm32-y += milkymist-pfpu.o obj-lm32-y += milkymist-softusb.o obj-lm32-y += milkymist-sysctl.o obj-lm32-$(CONFIG_OPENGL) += milkymist-tmu2.o +obj-lm32-y += milkymist-uart.o obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o obj-mips-y += mips_addr.o mips_timer.o mips_int.o diff --git a/hw/milkymist-uart.c b/hw/milkymist-uart.c new file mode 100644 index 0000000..56c90da --- /dev/null +++ b/hw/milkymist-uart.c @@ -0,0 +1,180 @@ +/* + * QEMU model of the Milkymist UART block. + * + * Copyright (c) 2010 Michael Walle + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + * + * Specification available at: + * http://www.milkymist.org/socdoc/uart.pdf + */ + +#include "hw.h" +#include "sysbus.h" +#include "trace.h" +#include "qemu-char.h" +#include "qemu-error.h" + +enum { + R_RXTX = 0, + R_DIV, + R_MAX +}; + +struct MilkymistUartState { + SysBusDevice busdev; + CharDriverState *chr; + qemu_irq rx_irq; + qemu_irq tx_irq; + + uint32_t regs[R_MAX]; +}; +typedef struct MilkymistUartState MilkymistUartState; + +static uint32_t uart_read(void *opaque, target_phys_addr_t addr) +{ + MilkymistUartState *s = opaque; + uint32_t r = 0; + + addr >>= 2; + switch (addr) { + case R_RXTX: + case R_DIV: + r = s->regs[addr]; + break; + + default: + error_report("milkymist_uart: read access to unknown register 0x" + TARGET_FMT_plx, addr << 2); + break; + } + + trace_milkymist_uart_memory_read(addr << 2, r); + + return r; +} + +static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value) +{ + MilkymistUartState *s = opaque; + unsigned char ch = value; + + trace_milkymist_uart_memory_write(addr, value); + + addr >>= 2; + switch (addr) { + case R_RXTX: + if (s->chr) { + qemu_chr_write(s->chr, &ch, 1); + } + trace_milkymist_uart_pulse_irq_tx(); + qemu_irq_pulse(s->tx_irq); + break; + case R_DIV: + s->regs[addr] = value; + break; + + default: + error_report("milkymist_uart: write access to unknown register 0x" + TARGET_FMT_plx, addr << 2); + break; + } +} + +static CPUReadMemoryFunc * const uart_read_fn[] = { + NULL, + NULL, + &uart_read, +}; + +static CPUWriteMemoryFunc * const uart_write_fn[] = { + NULL, + NULL, + &uart_write, +}; + +static void uart_rx(void *opaque, const uint8_t *buf, int size) +{ + MilkymistUartState *s = opaque; + + s->regs[R_RXTX] = *buf; + trace_milkymist_uart_pulse_irq_rx(); + qemu_irq_pulse(s->rx_irq); +} + +static int uart_can_rx(void *opaque) +{ + return 1; +} + +static void uart_event(void *opaque, int event) +{ +} + +static void milkymist_uart_reset(DeviceState *d) +{ + MilkymistUartState *s = container_of(d, MilkymistUartState, busdev.qdev); + int i; + + for (i = 0; i < R_MAX; i++) { + s->regs[i] = 0; + } +} + +static int milkymist_uart_init(SysBusDevice *dev) +{ + MilkymistUartState *s = FROM_SYSBUS(typeof(*s), dev); + int uart_regs; + + sysbus_init_irq(dev, &s->rx_irq); + sysbus_init_irq(dev, &s->tx_irq); + + uart_regs = cpu_register_io_memory(uart_read_fn, uart_write_fn, s, + DEVICE_NATIVE_ENDIAN); + sysbus_init_mmio(dev, R_MAX * 4, uart_regs); + + s->chr = qdev_init_chardev(&dev->qdev); + if (s->chr) { + qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s); + } + + return 0; +} + +static const VMStateDescription vmstate_milkymist_uart = { + .name = "milkymist-uart", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, MilkymistUartState, R_MAX), + VMSTATE_END_OF_LIST() + } +}; + +static SysBusDeviceInfo milkymist_uart_info = { + .init = milkymist_uart_init, + .qdev.name = "milkymist-uart", + .qdev.size = sizeof(MilkymistUartState), + .qdev.vmsd = &vmstate_milkymist_uart, + .qdev.reset = milkymist_uart_reset, +}; + +static void milkymist_uart_register(void) +{ + sysbus_register_withprop(&milkymist_uart_info); +} + +device_init(milkymist_uart_register) diff --git a/trace-events b/trace-events index 85b6b21..1e574c4 100644 --- a/trace-events +++ b/trace-events @@ -346,3 +346,9 @@ disable milkymist_tmu2_memory_read(uint32_t addr, uint32_t value) "addr %08x val disable milkymist_tmu2_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x" disable milkymist_tmu2_start(void) "Start TMU" disable milkymist_tmu2_pulse_irq(void) "Pulse IRQ" + +# hw/milkymist-uart.c +disable milkymist_uart_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x" +disable milkymist_uart_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x" +disable milkymist_uart_pulse_irq_rx(void) "Pulse IRQ RX" +disable milkymist_uart_pulse_irq_tx(void) "Pulse IRQ TX"