From patchwork Mon Mar 7 22:32:33 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 85827 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CA631B70E7 for ; Tue, 8 Mar 2011 09:41:10 +1100 (EST) Received: from localhost ([127.0.0.1]:45964 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pwj50-0001GX-Mo for incoming@patchwork.ozlabs.org; Mon, 07 Mar 2011 17:39:06 -0500 Received: from [140.186.70.92] (port=55154 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PwizB-0006qy-J2 for qemu-devel@nongnu.org; Mon, 07 Mar 2011 17:33:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pwiz7-0003p9-IB for qemu-devel@nongnu.org; Mon, 07 Mar 2011 17:33:05 -0500 Received: from mail.serverraum.org ([78.47.150.89]:40944) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pwiz7-0003oo-7W for qemu-devel@nongnu.org; Mon, 07 Mar 2011 17:33:01 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.serverraum.org (Postfix) with ESMTP id CE17A3EF08; Mon, 7 Mar 2011 23:33:00 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at mail.serverraum.org Received: from mail.serverraum.org ([127.0.0.1]) by localhost (web.serverraum.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1xlf9OrmTISi; Mon, 7 Mar 2011 23:33:00 +0100 (CET) Received: from thanatos.fritz.box (91-67-5-72-dynip.superkabel.de [91.67.5.72]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.serverraum.org (Postfix) with ESMTPSA id 7ADDB3EEFA; Mon, 7 Mar 2011 23:33:00 +0100 (CET) From: Michael Walle To: qemu-devel@nongnu.org Date: Mon, 7 Mar 2011 23:32:33 +0100 Message-Id: <1299537165-16711-3-git-send-email-michael@walle.cc> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1299537165-16711-1-git-send-email-michael@walle.cc> References: <1299537165-16711-1-git-send-email-michael@walle.cc> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 78.47.150.89 Cc: "Edgar E. Iglesias" , Michael Walle , Alexander Graf Subject: [Qemu-devel] [PATCH 02/14] lm32: add Milkymist HPDMC support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds support for the Milkymist's High Performance Dynamic Memory Controller. This is just a dumb model without any functionality. While the real hardware acts for example as a bridge between software and hardware for sending SDRAM commans, this model will only eat up these commands and always returns the expected hardware states, eg. PLL locked etc. Signed-off-by: Michael Walle --- Makefile.target | 1 + hw/milkymist-hpdmc.c | 161 ++++++++++++++++++++++++++++++++++++++++++++++++++ trace-events | 4 + 3 files changed, 166 insertions(+), 0 deletions(-) create mode 100644 hw/milkymist-hpdmc.c diff --git a/Makefile.target b/Makefile.target index 3be7868..57902eb 100644 --- a/Makefile.target +++ b/Makefile.target @@ -257,6 +257,7 @@ obj-lm32-y += lm32_timer.o obj-lm32-y += lm32_uart.o obj-lm32-y += lm32_sys.o obj-lm32-y += milkymist-ac97.o +obj-lm32-y += milkymist-hpdmc.o obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o obj-mips-y += mips_addr.o mips_timer.o mips_int.o diff --git a/hw/milkymist-hpdmc.c b/hw/milkymist-hpdmc.c new file mode 100644 index 0000000..c0962fb --- /dev/null +++ b/hw/milkymist-hpdmc.c @@ -0,0 +1,161 @@ +/* + * QEMU model of the Milkymist High Performance Dynamic Memory Controller. + * + * Copyright (c) 2010 Michael Walle + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + * + * Specification available at: + * http://www.milkymist.org/socdoc/hpdmc.pdf + */ + +#include "hw.h" +#include "sysbus.h" +#include "trace.h" +#include "qemu-error.h" + +enum { + R_SYSTEM = 0, + R_BYPASS, + R_TIMING, + R_IODELAY, + R_MAX +}; + +enum { + IODELAY_DQSDELAY_RDY = (1<<5), + IODELAY_PLL1_LOCKED = (1<<6), + IODELAY_PLL2_LOCKED = (1<<7), +}; + +struct MilkymistHpdmcState { + SysBusDevice busdev; + + uint32_t regs[R_MAX]; +}; +typedef struct MilkymistHpdmcState MilkymistHpdmcState; + +static uint32_t hpdmc_read(void *opaque, target_phys_addr_t addr) +{ + MilkymistHpdmcState *s = opaque; + uint32_t r = 0; + + addr >>= 2; + switch (addr) { + case R_SYSTEM: + case R_BYPASS: + case R_TIMING: + case R_IODELAY: + r = s->regs[addr]; + break; + + default: + error_report("milkymist_hpdmc: read access to unknown register 0x" + TARGET_FMT_plx, addr << 2); + break; + } + + trace_milkymist_hpdmc_memory_read(addr << 2, r); + + return r; +} + +static void hpdmc_write(void *opaque, target_phys_addr_t addr, uint32_t value) +{ + MilkymistHpdmcState *s = opaque; + + trace_milkymist_hpdmc_memory_write(addr, value); + + addr >>= 2; + switch (addr) { + case R_SYSTEM: + case R_BYPASS: + case R_TIMING: + s->regs[addr] = value; + break; + case R_IODELAY: + /* ignore writes */ + break; + + default: + error_report("milkymist_hpdmc: write access to unknown register 0x" + TARGET_FMT_plx, addr << 2); + break; + } +} + +static CPUReadMemoryFunc * const hpdmc_read_fn[] = { + NULL, + NULL, + &hpdmc_read, +}; + +static CPUWriteMemoryFunc * const hpdmc_write_fn[] = { + NULL, + NULL, + &hpdmc_write, +}; + +static void milkymist_hpdmc_reset(DeviceState *d) +{ + MilkymistHpdmcState *s = container_of(d, MilkymistHpdmcState, busdev.qdev); + int i; + + for (i = 0; i < R_MAX; i++) { + s->regs[i] = 0; + } + + /* defaults */ + s->regs[R_IODELAY] = IODELAY_DQSDELAY_RDY | IODELAY_PLL1_LOCKED + | IODELAY_PLL2_LOCKED; +} + +static int milkymist_hpdmc_init(SysBusDevice *dev) +{ + MilkymistHpdmcState *s = FROM_SYSBUS(typeof(*s), dev); + int hpdmc_regs; + + hpdmc_regs = cpu_register_io_memory(hpdmc_read_fn, hpdmc_write_fn, s, + DEVICE_NATIVE_ENDIAN); + sysbus_init_mmio(dev, R_MAX * 4, hpdmc_regs); + + return 0; +} + +static const VMStateDescription vmstate_milkymist_hpdmc = { + .name = "milkymist-hpdmc", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, MilkymistHpdmcState, R_MAX), + VMSTATE_END_OF_LIST() + } +}; + +static SysBusDeviceInfo milkymist_hpdmc_info = { + .init = milkymist_hpdmc_init, + .qdev.name = "milkymist-hpdmc", + .qdev.size = sizeof(MilkymistHpdmcState), + .qdev.vmsd = &vmstate_milkymist_hpdmc, + .qdev.reset = milkymist_hpdmc_reset, +}; + +static void milkymist_hpdmc_register(void) +{ + sysbus_register_withprop(&milkymist_hpdmc_info); +} + +device_init(milkymist_hpdmc_register) diff --git a/trace-events b/trace-events index 9241ac9..afed656 100644 --- a/trace-events +++ b/trace-events @@ -295,3 +295,7 @@ disable milkymist_ac97_in_cb(int avail, uint32_t remaining) "avail %d remaining disable milkymist_ac97_in_cb_transferred(int transferred) "transferred %d" disable milkymist_ac97_out_cb(int free, uint32_t remaining) "free %d remaining %u" disable milkymist_ac97_out_cb_transferred(int transferred) "transferred %d" + +# hw/milkymist-hpdmc.c +disable milkymist_hpdmc_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x" +disable milkymist_hpdmc_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"