From patchwork Wed Jan 10 12:11:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 858239 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="VqDewkfm"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zGntn4lq8z9ryk for ; Wed, 10 Jan 2018 23:12:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932915AbeAJMMA (ORCPT ); Wed, 10 Jan 2018 07:12:00 -0500 Received: from mail-qt0-f194.google.com ([209.85.216.194]:46651 "EHLO mail-qt0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932899AbeAJML7 (ORCPT ); Wed, 10 Jan 2018 07:11:59 -0500 Received: by mail-qt0-f194.google.com with SMTP id r39so21691531qtr.13 for ; Wed, 10 Jan 2018 04:11:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=3kaosHHSAgURlZBr7Xx0X7HbaOumD1pvVZpWI6HrM2M=; b=VqDewkfmJlXe7kRwF4FG6wMIHGwK8tS9sMy5Bvy7d+X+DE5uwXiE/6bPm2qlvhg83B SrKaiy9Tf30r7aKMdKpDMWKvg8aFMUL/NnbgZEv1bY8qCw8z4KZGbtrpsGK9W8X091gp 2nHvSrL736yAno0uZpqObPTp2D5OH5Z8/vuk48LyjcsB3lhVGLUy/+TIn0fuprNUd/pO Czhhxm6SPVHMPfzA1UNrTEvpfL8lTAed2sWxhHq9mHJoarec1PeJX9HExxsyo/HgXfrB Gejtxn6y8f35hHrqQt5vwDuYOtoV8KR01uqa7aNQTbb5B+ntUSWcAgTrVZTsVivm2gHB Dzpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=3kaosHHSAgURlZBr7Xx0X7HbaOumD1pvVZpWI6HrM2M=; b=Dx7RA0oZjUoBAaXs6F2RLdNi6j91r42P1Du+dGmW3qb5dT64R0MLA/0L28JGhLQv+G 5umDEduiGt68/yyXUpKNZjzR0lfdyKhBpS5RFtmshJaBSFfNo59ISHJQDEQbLxDElKHo QV2wbTGwYVqICSWKWElLGWMuARP0ET9zAlxZwQ+oXGYPd538vI4Rbx+Bk8IXFtG/7pCm SQ5eKfDQypdyuwLacyUeBnkJ5V+9O6j1NpGI5/ln/bnea+vSci6b9vvz82irgH5xoWN7 UA/s7JKB0iC4gAWI3oF2Fohr4xTqjaKtTo9wumx8V85AAgkip0Hsp6KL/Mxaa4ibGEJz 4RDw== X-Gm-Message-State: AKwxytdCchfclYS7ClBzRA6QulS3FUZ4CwUOwxqoiqUQ7IblLE+RIMEN Nn4PlSCVF6vpJFbRLkB4Tzg= X-Google-Smtp-Source: ACJfBos/sCwn9Zz84Pg1GlnDb3W6JK2RlV7HpsB3hF8YRdSeMbDtXqwzjjTGeB0vzfWbE5N3QE2AWQ== X-Received: by 10.200.2.73 with SMTP id o9mr26463881qtg.46.1515586318803; Wed, 10 Jan 2018 04:11:58 -0800 (PST) Received: from localhost (p200300E41F1A2D00C4E4B29839822A7C.dip0.t-ipconnect.de. [2003:e4:1f1a:2d00:c4e4:b298:3982:2a7c]) by smtp.gmail.com with ESMTPSA id z8sm10535066qta.81.2018.01.10.04.11.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 10 Jan 2018 04:11:58 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jonathan Hunter , Guillaume Tucker , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH] drm/tegra: sor: Fix hang on Tegra124 eDP Date: Wed, 10 Jan 2018 13:11:55 +0100 Message-Id: <20180110121155.26345-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.15.1 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The SOR0 found on Tegra124 and Tegra210 only supports eDP and LVDS and therefore has a slightly different clock tree than the SOR1 which does not support eDP, but HDMI and DP instead. Commit e1335e2f0cfc ("drm/tegra: sor: Reimplement pad clock") breaks setups with eDP because the sor->clk_out clock is uninitialized and therefore setting the parent clock (either the safe clock or either of the display PLLs) fails, which can cause hangs later on since there is no clock driving the module. Fix this by falling back to the module clock for sor->clk_out on those setups. This guarantees that the module will always be clocked by an enabled clock and hence prevents those hangs. Fixes: e1335e2f0cfc ("drm/tegra: sor: Reimplement pad clock") Reported-by: Guillaume Tucker Tested-by: Jon Hunter Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index b0a1dedac802..476079f1255f 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -2656,6 +2656,9 @@ static int tegra_sor_probe(struct platform_device *pdev) name, err); goto remove; } + } else { + /* fall back to the module clock on SOR0 (eDP/LVDS only) */ + sor->clk_out = sor->clk; } sor->clk_parent = devm_clk_get(&pdev->dev, "parent");