From patchwork Tue Jan 9 07:17:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Preetham Chandru Ramchandra X-Patchwork-Id: 857272 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zG3QV3MyZz9sBZ for ; Tue, 9 Jan 2018 18:18:26 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933035AbeAIHSZ (ORCPT ); Tue, 9 Jan 2018 02:18:25 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:12091 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932850AbeAIHSY (ORCPT ); Tue, 9 Jan 2018 02:18:24 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 08 Jan 2018 23:18:37 -0800 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 08 Jan 2018 23:18:24 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 08 Jan 2018 23:18:24 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 9 Jan 2018 07:18:24 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 9 Jan 2018 07:18:20 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Tue, 9 Jan 2018 07:18:20 +0000 Received: from pchandru-pc.nvidia.com (Not Verified[10.24.37.8]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 08 Jan 2018 23:18:19 -0800 From: Preetham Chandru Ramchandra To: , , CC: , , , , , Preetham Ramchandra Subject: [PATCH V6 5/7] ata: ahci_tegra: disable devslp for t124 Date: Tue, 9 Jan 2018 12:47:12 +0530 Message-ID: <1515482234-24716-6-git-send-email-pchandru@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515482234-24716-1-git-send-email-pchandru@nvidia.com> References: <1515482234-24716-1-git-send-email-pchandru@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org From: Preetham Ramchandra t124 does not support devslp and it should be disabled. Signed-off-by: Preetham Chandru R Reviewed-by: Mikko Perttunen --- drivers/ata/ahci_tegra.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c index 90dfa803607e..a59a97b1b2e5 100644 --- a/drivers/ata/ahci_tegra.c +++ b/drivers/ata/ahci_tegra.c @@ -145,6 +145,10 @@ #define FUSE_SATA_CALIB 0x124 #define FUSE_SATA_CALIB_MASK 0x3 +enum { + NO_DEVSLP = (1 << 0), +}; + struct sata_pad_calibration { u8 gen1_tx_amp; u8 gen1_tx_peak; @@ -166,12 +170,14 @@ struct tegra_ahci_ops { struct tegra_ahci_soc { const char *const *supply_names; u32 num_supplies; + u32 quirks; struct tegra_ahci_ops ops; }; struct tegra_ahci_priv { struct platform_device *pdev; void __iomem *sata_regs; + void __iomem *sata_aux_regs; struct reset_control *sata_rst; struct reset_control *sata_oob_rst; struct reset_control *sata_cold_rst; @@ -185,6 +191,18 @@ static const char *const tegra124_supply_names[] = { "avdd", "hvdd", "vddio", "target-5v", "target-12v" }; +static void tegra_ahci_handle_quirks(struct ahci_host_priv *hpriv) +{ + struct tegra_ahci_priv *tegra = hpriv->plat_data; + u32 val; + + if (tegra->sata_aux_regs && (tegra->soc_data->quirks & NO_DEVSLP)) { + val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); + val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT; + writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); + } +} + static int tegra124_ahci_init(struct ahci_host_priv *hpriv) { struct tegra_ahci_priv *tegra = hpriv->plat_data; @@ -232,6 +250,7 @@ static int tegra124_ahci_init(struct ahci_host_priv *hpriv) static const struct tegra_ahci_soc tegra124_ahci_soc_data = { .supply_names = tegra124_supply_names, .num_supplies = ARRAY_SIZE(tegra124_supply_names), + .quirks = NO_DEVSLP, .ops = { .init = tegra124_ahci_init, }, @@ -412,6 +431,7 @@ static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv) val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE; writel(val, tegra->sata_regs + SATA_CONFIGURATION_0); + tegra_ahci_handle_quirks(hpriv); /* Unmask SATA interrupts */ @@ -485,6 +505,15 @@ static int tegra_ahci_probe(struct platform_device *pdev) tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(tegra->sata_regs)) return PTR_ERR(tegra->sata_regs); + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + /* + * Aux register is optional. + */ + if (res) { + tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(tegra->sata_aux_regs)) + return PTR_ERR(tegra->sata_aux_regs); + } tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata"); if (IS_ERR(tegra->sata_rst)) {