From patchwork Mon Jan 8 11:53:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 856778 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zFYZZ31ddz9s9Y for ; Mon, 8 Jan 2018 22:53:42 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zFYZY6MTRzF0Sg for ; Mon, 8 Jan 2018 22:53:41 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zFYZM4tFHzF0RZ for ; Mon, 8 Jan 2018 22:53:30 +1100 (AEDT) Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.21) with SMTP id w08BpZY9010329 for ; Mon, 8 Jan 2018 06:53:28 -0500 Received: from e06smtp15.uk.ibm.com (e06smtp15.uk.ibm.com [195.75.94.111]) by mx0b-001b2d01.pphosted.com with ESMTP id 2fc32sef1q-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 08 Jan 2018 06:53:27 -0500 Received: from localhost by e06smtp15.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 8 Jan 2018 11:53:24 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w08BrNfR64028800; Mon, 8 Jan 2018 11:53:23 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EDDA2A404D; Mon, 8 Jan 2018 11:47:17 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B6E63A405B; Mon, 8 Jan 2018 11:47:16 +0000 (GMT) Received: from vajain21.in.ibm.com (unknown [9.124.35.190]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 8 Jan 2018 11:47:16 +0000 (GMT) From: Vaibhav Jain To: stewart@linux.vnet.ibm.com, Russell Currey , Christophe Lombard Date: Mon, 8 Jan 2018 17:23:05 +0530 X-Mailer: git-send-email 2.14.3 X-TM-AS-GCONF: 00 x-cbid: 18010811-0020-0000-0000-000003E80194 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18010811-0021-0000-0000-0000427A1D41 Message-Id: <20180108115305.9998-1-vaibhav@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-08_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801080172 Subject: [Skiboot] [PATCH] phb4: Dump CAPP error registers when it asserts link down X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Donnellan , skiboot@lists.ozlabs.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This patch introduces a new function phb4_dump_app_err_regs() that dumps CAPP error registers in case the PEC nestfir register indicates that the fence was due to a CAPP error (BIT-24). Contents of these registers are helpful in diagnosing CAPP issues. Registers that are dumped in phb4_dump_app_err_regs() are: * CAPP FIR Register * CAPP APC Master Error Report Register * CAPP Snoop Error Report Register * CAPP Transport Error Report Register * CAPP TLBI Error Report Register * CAPP Error Status and Control Register Signed-off-by: Vaibhav Jain Reviewed-by: Andrew Donnellan Reviewed-by: Christophe Lombard Acked-by: Russell Currey --- hw/phb4.c | 36 +++++++++++++++++++++++++++++++----- include/phb4-capp.h | 8 ++++++-- include/phb4-regs.h | 1 + 3 files changed, 38 insertions(+), 7 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 6c59462b..ff912e1f 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -2338,6 +2338,28 @@ static void phb4_train_info(struct phb4 *p, uint64_t reg, unsigned long time) PHBERR(p, "%s\n", s); } +static void phb4_dump_capp_err_regs(struct phb4 *p) +{ + uint64_t fir, apc_master_err, snoop_err, transport_err; + uint64_t tlbi_err, capp_err_status; + uint64_t offset = PHB4_CAPP_REG_OFFSET(p); + + xscom_read(p->chip_id, CAPP_FIR + offset, &fir); + xscom_read(p->chip_id, CAPP_APC_MASTER_ERR_RPT + offset, + &apc_master_err); + xscom_read(p->chip_id, CAPP_SNOOP_ERR_RTP + offset, &snoop_err); + xscom_read(p->chip_id, CAPP_TRANSPORT_ERR_RPT + offset, &transport_err); + xscom_read(p->chip_id, CAPP_TLBI_ERR_RPT + offset, &tlbi_err); + xscom_read(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, &capp_err_status); + + PHBERR(p, " CAPP FIR=%016llx\n", fir); + PHBERR(p, "CAPP APC MASTER ERR=%016llx\n", apc_master_err); + PHBERR(p, " CAPP SNOOP ERR=%016llx\n", snoop_err); + PHBERR(p, " CAPP TRANSPORT ERR=%016llx\n", transport_err); + PHBERR(p, " CAPP TLBI ERR=%016llx\n", tlbi_err); + PHBERR(p, " CAPP ERR STATUS=%016llx\n", capp_err_status); +} + /* Check if AIB is fenced via PBCQ NFIR */ static bool phb4_fenced(struct phb4 *p) { @@ -2369,16 +2391,20 @@ static bool phb4_fenced(struct phb4 *p) xscom_read(p->chip_id, p->pci_stk_xscom + XPEC_PCI_STK_PBAIB_ERR_REPORT, &err_aib); - PHBERR(p, " PCI FIR=%016llx\n", nfir_p); - PHBERR(p, "NEST FIR=%016llx\n", nfir_n); - PHBERR(p, "ERR RPT0=%016llx\n", err_rpt0); - PHBERR(p, "ERR RPT1=%016llx\n", err_rpt1); - PHBERR(p, " AIB ERR=%016llx\n", err_aib); + PHBERR(p, " PCI FIR=%016llx\n", nfir_p); + PHBERR(p, " NEST FIR=%016llx\n", nfir_n); + PHBERR(p, " ERR RPT0=%016llx\n", err_rpt0); + PHBERR(p, " ERR RPT1=%016llx\n", err_rpt1); + PHBERR(p, " AIB ERR=%016llx\n", err_aib); /* Mark ourselves fenced */ p->flags |= PHB4_AIB_FENCED; p->state = PHB4_STATE_FENCED; + /* dump capp error registers in case phb was fenced due to capp */ + if (nfir_n & XPEC_NEST_STK_PCI_NFIR_CXA_PE_CAPP) + phb4_dump_capp_err_regs(p); + phb4_eeh_dump_regs(p); return true; diff --git a/include/phb4-capp.h b/include/phb4-capp.h index 10cdc406..68200ac5 100644 --- a/include/phb4-capp.h +++ b/include/phb4-capp.h @@ -26,6 +26,12 @@ #define CAPP_FIR_MASK 0x2010803 #define CAPP_FIR_ACTION0 0x2010806 #define CAPP_FIR_ACTION1 0x2010807 +#define CAPP_SNOOP_ERR_RTP 0x201080A +#define CAPP_APC_MASTER_ERR_RPT 0x201080B +#define CAPP_TRANSPORT_ERR_RPT 0x201080C +#define CAPP_TLBI_ERR_RPT 0x201080D +#define CAPP_ERR_STATUS_CTRL 0x201080E +#define FLUSH_SUE_STATE_MAP 0x201080F #define CAPP_ERR_RPT_CLR 0x2010813 #define APC_MASTER_PB_CTRL 0x2010818 #define APC_MASTER_CAPI_CTRL 0x2010819 @@ -36,8 +42,6 @@ #define TRANSPORT_CONTROL 0x201081C #define CAPP_TB 0x2010826 #define CAPP_TFMR 0x2010827 -#define CAPP_ERR_STATUS_CTRL 0x201080E -#define FLUSH_SUE_STATE_MAP 0x201080F #define FLUSH_CPIG_STATE_MAP 0x2010820 #define FLUSH_SUE_UOP1 0x2010843 /* Satellite 2 */ #define APC_FSM_READ_MASK 0x2010823 diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 0d8aa48b..2dc64fe5 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -343,6 +343,7 @@ /* Nest base per-stack registers */ #define XPEC_NEST_STK_PCI_NFIR 0x0 +#define XPEC_NEST_STK_PCI_NFIR_CXA_PE_CAPP PPC_BIT(24) #define XPEC_NEST_STK_PCI_NFIR_CLR 0x1 #define XPEC_NEST_STK_PCI_NFIR_SET 0x2 #define XPEC_NEST_STK_PCI_NFIR_MSK 0x3