Message ID | 20180106181802.9298-2-jarush@gmail.com |
---|---|
State | Changes Requested |
Delegated to: | Jagannadha Sutradharudu Teki |
Headers | show |
Series | spi: cadence_spi: Adopt Linux DT bindings | expand |
On Sat, Jan 6, 2018 at 11:47 PM, Jason Rush <jarush@gmail.com> wrote: > Adopt the Linux DT bindings. This also fixes an issue > with the indaddrtrig register on the Cadence QSPI > device being programmed with the wrong value for the > socfpga arch. > > Tested on TI K2G platform: > Tested-by: Vignesh R <vigneshr@ti.com> > > Tested on a socfpga-cyclonev board: > Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> > > Signed-off-by: Jason Rush <jarush@gmail.com> > Cc: Marek Vasut <marex@denx.de> > --- > Changes for v5: > - Rebased > Changes for v4: > - Rebased > Changes for v3: > - None > > drivers/spi/cadence_qspi.c | 20 ++++++++++++-------- > drivers/spi/cadence_qspi.h | 6 +++++- > drivers/spi/cadence_qspi_apb.c | 15 ++++----------- > 3 files changed, 21 insertions(+), 20 deletions(-) > > diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c > index 9a6e41f330..991a7160bd 100644 > --- a/drivers/spi/cadence_qspi.c > +++ b/drivers/spi/cadence_qspi.c > @@ -212,7 +212,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen, > > /* Set Chip select */ > cadence_qspi_apb_chipselect(base, spi_chip_select(dev), > - CONFIG_CQSPI_DECODER); > + plat->is_decoded_cs); > > if ((flags & SPI_XFER_END) || (flags == 0)) { > if (priv->cmd_len == 0) { > @@ -296,7 +296,11 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) > > plat->regbase = (void *)data[0]; > plat->ahbbase = (void *)data[2]; > - plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); > + plat->is_decoded_cs = fdtdec_get_bool(blob, node, "cdns,is-decoded-cs"); > + plat->fifo_depth = fdtdec_get_uint(blob, node, "cdns,fifo-depth", 128); > + plat->fifo_width = fdtdec_get_uint(blob, node, "cdns,fifo-width", 4); > + plat->trigger_address = fdtdec_get_uint(blob, node, > + "cdns,trigger-address", 0); fix these checkpatch warnings. > > /* All other paramters are embedded in the child node */ > subnode = fdt_first_subnode(blob, node); > @@ -310,12 +314,12 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) > 500000); > > /* Read other parameters from DT */ > - plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256); > - plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16); > - plat->tshsl_ns = fdtdec_get_int(blob, subnode, "tshsl-ns", 200); > - plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255); > - plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20); > - plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); > + plat->page_size = fdtdec_get_uint(blob, subnode, "page-size", 256); > + plat->block_size = fdtdec_get_uint(blob, subnode, "block-size", 16); > + plat->tshsl_ns = fdtdec_get_uint(blob, subnode, "cdns,tshsl-ns", 200); > + plat->tsd2d_ns = fdtdec_get_uint(blob, subnode, "cdns,tsd2d-ns", 255); > + plat->tchsh_ns = fdtdec_get_uint(blob, subnode, "cdns,tchsh-ns", 20); > + plat->tslch_ns = fdtdec_get_uint(blob, subnode, "cdns,tslch-ns", 20); > > debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", > __func__, plat->regbase, plat->ahbbase, plat->max_hz, > diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h > index d1927a4003..83154210bd 100644 > --- a/drivers/spi/cadence_qspi.h > +++ b/drivers/spi/cadence_qspi.h > @@ -18,14 +18,18 @@ struct cadence_spi_platdata { > unsigned int max_hz; > void *regbase; > void *ahbbase; > + bool is_decoded_cs; > + u32 fifo_depth; > + u32 fifo_width; > + u32 trigger_address; > > + // Flash parameters fix with proper single line comment /* ... */ except these, Reviewed-by: Jagan Teki <jagan@openedev.com>
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 9a6e41f330..991a7160bd 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -212,7 +212,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen, /* Set Chip select */ cadence_qspi_apb_chipselect(base, spi_chip_select(dev), - CONFIG_CQSPI_DECODER); + plat->is_decoded_cs); if ((flags & SPI_XFER_END) || (flags == 0)) { if (priv->cmd_len == 0) { @@ -296,7 +296,11 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->regbase = (void *)data[0]; plat->ahbbase = (void *)data[2]; - plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); + plat->is_decoded_cs = fdtdec_get_bool(blob, node, "cdns,is-decoded-cs"); + plat->fifo_depth = fdtdec_get_uint(blob, node, "cdns,fifo-depth", 128); + plat->fifo_width = fdtdec_get_uint(blob, node, "cdns,fifo-width", 4); + plat->trigger_address = fdtdec_get_uint(blob, node, + "cdns,trigger-address", 0); /* All other paramters are embedded in the child node */ subnode = fdt_first_subnode(blob, node); @@ -310,12 +314,12 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) 500000); /* Read other parameters from DT */ - plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256); - plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16); - plat->tshsl_ns = fdtdec_get_int(blob, subnode, "tshsl-ns", 200); - plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255); - plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20); - plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); + plat->page_size = fdtdec_get_uint(blob, subnode, "page-size", 256); + plat->block_size = fdtdec_get_uint(blob, subnode, "block-size", 16); + plat->tshsl_ns = fdtdec_get_uint(blob, subnode, "cdns,tshsl-ns", 200); + plat->tsd2d_ns = fdtdec_get_uint(blob, subnode, "cdns,tsd2d-ns", 255); + plat->tchsh_ns = fdtdec_get_uint(blob, subnode, "cdns,tchsh-ns", 20); + plat->tslch_ns = fdtdec_get_uint(blob, subnode, "cdns,tslch-ns", 20); debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", __func__, plat->regbase, plat->ahbbase, plat->max_hz, diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index d1927a4003..83154210bd 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -18,14 +18,18 @@ struct cadence_spi_platdata { unsigned int max_hz; void *regbase; void *ahbbase; + bool is_decoded_cs; + u32 fifo_depth; + u32 fifo_width; + u32 trigger_address; + // Flash parameters u32 page_size; u32 block_size; u32 tshsl_ns; u32 tsd2d_ns; u32 tchsh_ns; u32 tslch_ns; - u32 sram_size; }; struct cadence_spi_priv { diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e02f2217f4..8309ab8794 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -37,10 +37,6 @@ #define CQSPI_REG_RETRY 10000 #define CQSPI_POLL_IDLE_RETRY 3 -#define CQSPI_FIFO_WIDTH 4 - -#define CQSPI_REG_SRAM_THRESHOLD_WORDS 50 - /* Transfer mode */ #define CQSPI_INST_TYPE_SINGLE 0 #define CQSPI_INST_TYPE_DUAL 1 @@ -51,9 +47,6 @@ #define CQSPI_DUMMY_CLKS_PER_BYTE 8 #define CQSPI_DUMMY_BYTES_MAX 4 -#define CQSPI_REG_SRAM_FILL_THRESHOLD \ - ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH) - /**************************************************************************** * Controller's configuration and status register (offset from QSPI_BASE) ****************************************************************************/ @@ -400,7 +393,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) writel(0, plat->regbase + CQSPI_REG_REMAP); /* Indirect mode configurations */ - writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION); + writel((plat->fifo_depth/2), plat->regbase + CQSPI_REG_SRAMPARTITION); /* Disable all interrupts */ writel(0, plat->regbase + CQSPI_REG_IRQMASK); @@ -560,7 +553,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, addr_bytes = cmdlen - 1; /* Setup the indirect trigger address */ - writel((u32)plat->ahbbase, + writel(plat->trigger_address, plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */ @@ -659,7 +652,7 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, bytes_to_read = ret; while (bytes_to_read != 0) { - bytes_to_read *= CQSPI_FIFO_WIDTH; + bytes_to_read *= plat->fifo_width; bytes_to_read = bytes_to_read > remaining ? remaining : bytes_to_read; readsl(plat->ahbbase, bb_rxbuf, bytes_to_read >> 2); @@ -710,7 +703,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, return -EINVAL; } /* Setup the indirect trigger address */ - writel((u32)plat->ahbbase, + writel(plat->trigger_address, plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */