From patchwork Sat Jan 6 16:58:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 856420 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=crapouillou.net header.i=@crapouillou.net header.b="rQEuQ6GK"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zDSfp100bz9s7c for ; Sun, 7 Jan 2018 04:08:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753663AbeAFRIb (ORCPT ); Sat, 6 Jan 2018 12:08:31 -0500 Received: from outils.crapouillou.net ([89.234.176.41]:34204 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753638AbeAFRIa (ORCPT ); Sat, 6 Jan 2018 12:08:30 -0500 From: Paul Cercueil To: Thierry Reding , Rob Herring , Mark Rutland Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Maarten ter Huurne Subject: [PATCH 1/4] pwm: jz4740: Make disable operation compatible with TCU2 mode Date: Sat, 6 Jan 2018 17:58:40 +0100 Message-Id: <20180106165843.3461-1-paul@crapouillou.net> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1515257929; bh=Z/V0rR5mEsXBDn8LNrAnaYwMf/oBidK5dJeLYg1mWas=; h=From:To:Cc:Subject:Date:Message-Id; b=rQEuQ6GKs/ADPfZ87SXUFXKKL/K58U8R5TLDR9QLpxLbQY2OR/4LKE4LzbQJMUqJ5hMPWt58cnD7JngJY+bgyekgyPaYYPf5+s9BaLDTuqdzFs5lxRcllE0w7gUDj5mKmYbavbdf4VQ1v4n17IHopahUkbc1JHuAJxl2y2zDbd0= Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Maarten ter Huurne On the JZ4750 and later SoCs, channel 1 and 2 operate in a different way (TCU2 mode) as the other channels. If a TCU2 mode counter is stopped before its PWM functionality is disabled, the output is not guaranteed to return to the initial level. Signed-off-by: Maarten ter Huurne --- drivers/pwm/pwm-jz4740.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c index a75ff3622450..2e41ba213f39 100644 --- a/drivers/pwm/pwm-jz4740.c +++ b/drivers/pwm/pwm-jz4740.c @@ -71,9 +71,15 @@ static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { uint32_t ctrl = jz4740_timer_get_ctrl(pwm->hwpwm); + /* Disable PWM output. + * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the + * counter is stopped, while in TCU1 mode the order does not matter. + */ ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE; - jz4740_timer_disable(pwm->hwpwm); jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); + + /* Stop counter */ + jz4740_timer_disable(pwm->hwpwm); } static int jz4740_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,