Message ID | 151520102116.32271.8160376567325482844.stgit@dwillia2-desk3.amr.corp.intel.com |
---|---|
State | Not Applicable, archived |
Delegated to: | David Miller |
Headers | show |
Series | prevent bounds-check bypass via speculative execution | expand |
diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h index 7fb336210e1b..1148cd9f5ae7 100644 --- a/arch/x86/include/asm/barrier.h +++ b/arch/x86/include/asm/barrier.h @@ -24,6 +24,12 @@ #define wmb() asm volatile("sfence" ::: "memory") #endif +/* + * CPUs without LFENCE don't really speculate much. Possibly fall back to IRET-to-self. + */ +#define __nospec_barrier() alternative("", "lfence", X86_FEATURE_LFENCE_RDTSC) +#define nospec_barrier __nospec_barrier + #ifdef CONFIG_X86_PPRO_FENCE #define dma_rmb() rmb() #else