From patchwork Thu Jan 4 11:27:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 855566 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zC5Gb02qxz9sRm for ; Thu, 4 Jan 2018 22:31:19 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zC5GZ5N50zDqxR for ; Thu, 4 Jan 2018 22:31:18 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=akshay.adiga@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zC5Cd1b5xzDr5W for ; Thu, 4 Jan 2018 22:28:45 +1100 (AEDT) Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w04BSgSE045840 for ; Thu, 4 Jan 2018 06:28:43 -0500 Received: from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110]) by mx0a-001b2d01.pphosted.com with ESMTP id 2f9hvvc2yu-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 04 Jan 2018 06:28:42 -0500 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 Jan 2018 11:28:19 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w04BSIj544433636; Thu, 4 Jan 2018 11:28:19 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 462B311C05B; Thu, 4 Jan 2018 11:22:16 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2F86E11C04C; Thu, 4 Jan 2018 11:22:15 +0000 (GMT) Received: from aksadiga.in.ibm.com (unknown [9.77.193.244]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 4 Jan 2018 11:22:14 +0000 (GMT) From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Thu, 4 Jan 2018 16:57:59 +0530 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> References: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18010411-0016-0000-0000-000005139ABF X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18010411-0017-0000-0000-0000284FE6DD Message-Id: <1515065286-8656-3-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-04_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801040159 Subject: [Skiboot] [PATCH 2/9] SLW: Split init functions X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This patch seperates code which deals with wakeup_engine from one which doesn't. Init functions for power8 and power9 are split into chip_init and late_init. slw_late_init_p?() contains wakeup_engine related code. Signed-off-by: Akshay Adiga --- hw/slw.c | 75 +++++++++++++++++++++++++++++++++++++--------------------------- 1 file changed, 43 insertions(+), 32 deletions(-) diff --git a/hw/slw.c b/hw/slw.c index d6d140f8..2fdfa4e8 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -803,6 +803,36 @@ static struct cpu_idle_states power9_ndd1_cpu_idle_states[] = { | OPAL_PM_PSSCR_EC, .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK } }; +static void slw_late_init_p9(struct proc_chip *chip) +{ + struct cpu_thread *c; + int rc; + + if (!chip->homer_base) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: HOMER base not set %x\n", + chip->id); + return; + } + prlog(PR_NOTICE, "SLW: Configuring self-restore for HRMOR\n"); + for_each_available_cpu(c) { + if (c->chip_id != chip->id) + continue; + /* + * Clear HRMOR. Need to update only for thread + * 0 of each core. Doing it anyway for all threads + */ + rc = p9_stop_save_cpureg((void *)chip->homer_base, + P9_STOP_SPR_HRMOR, 0, + c->pir); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: Failed to set HRMOR for CPU %x,RC=0x%x\n", + c->pir, rc); + prlog(PR_ERR, "Disabling deep stop states\n"); + } + } +} /* Add device tree properties to describe idle states */ void add_cpu_idle_state_properties(void) @@ -1265,7 +1295,6 @@ static void slw_patch_regs(struct proc_chip *chip) static void slw_init_chip_p9(struct proc_chip *chip) { struct cpu_thread *c; - int rc; prlog(PR_DEBUG, "SLW: Init chip 0x%x\n", chip->id); @@ -1273,38 +1302,11 @@ static void slw_init_chip_p9(struct proc_chip *chip) for_each_available_core_in_chip(c, chip->id) slw_set_overrides_p9(chip, c); - if (!chip->homer_base) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: HOMER base not set %x\n", - chip->id); - return; - } - - prlog(PR_NOTICE, "SLW: Configuring self-restore for HRMOR\n"); - - /* Should this be for_each_present_cpu() ? */ - for_each_available_cpu(c) { - if (c->chip_id != chip->id) - continue; - /* - * Clear HRMOR. Need to update only for thread - * 0 of each core. Doing it anyway for all threads - */ - rc = p9_stop_save_cpureg((void *)chip->homer_base, - P9_STOP_SPR_HRMOR, 0, - c->pir); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: Failed to set HRMOR for CPU %x,RC=0x%x\n", - c->pir, rc); - } - } } -static void slw_init_chip(struct proc_chip *chip) +static void slw_late_init_p8(struct proc_chip *chip) { int64_t rc; - struct cpu_thread *c; prlog(PR_DEBUG, "SLW: Init chip 0x%x\n", chip->id); @@ -1337,6 +1339,11 @@ static void slw_init_chip(struct proc_chip *chip) /* Patch SLW image */ slw_patch_regs(chip); +} +static void slw_init_chip_p8(struct proc_chip *chip) +{ + struct cpu_thread *c; + /* At power ON setup inits for fast-sleep */ for_each_available_core_in_chip(c, chip->id) { idle_prepare_core(chip, c); @@ -1682,12 +1689,16 @@ void slw_init(void) struct proc_chip *chip; if (proc_gen == proc_gen_p8) { - for_each_chip(chip) - slw_init_chip(chip); + for_each_chip(chip) { + slw_init_chip_p8(chip); + slw_late_init_p8(chip); + } slw_init_timer(); } else if (proc_gen == proc_gen_p9) { - for_each_chip(chip) + for_each_chip(chip) { slw_init_chip_p9(chip); + slw_late_init_p9(chip); + } } add_cpu_idle_state_properties(); }