| Message ID | 1514783660-4290-1-git-send-email-jassisinghbrar@gmail.com |
|---|---|
| State | Changes Requested, archived |
| Delegated to: | David Miller |
| Headers | show |
| Series | Socionext Synquacer NETSEC driver | expand |
On Mon, Jan 01, 2018 at 10:44:20AM +0530, jassisinghbrar@gmail.com wrote: > From: Jassi Brar <jassisinghbrar@gmail.com> > > This patch adds documentation for Device-Tree bindings for the > Socionext NetSec Controller driver. > > Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > --- > .../devicetree/bindings/net/socionext-netsec.txt | 53 ++++++++++++++++++++++ > 1 file changed, 53 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/socionext-netsec.txt Reviewed-by: Rob Herring <robh@kernel.org>
Hi Jassi, On 1 January 2018 at 05:14, <jassisinghbrar@gmail.com> wrote: > From: Jassi Brar <jassisinghbrar@gmail.com> > > This patch adds documentation for Device-Tree bindings for the > Socionext NetSec Controller driver. > > Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > --- > .../devicetree/bindings/net/socionext-netsec.txt | 53 ++++++++++++++++++++++ > 1 file changed, 53 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/socionext-netsec.txt > > diff --git a/Documentation/devicetree/bindings/net/socionext-netsec.txt b/Documentation/devicetree/bindings/net/socionext-netsec.txt > new file mode 100644 > index 0000000..b70e35b > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/socionext-netsec.txt > @@ -0,0 +1,53 @@ > +* Socionext NetSec Ethernet Controller IP > + > +Required properties: > +- compatible: Should be "socionext,synquacer-netsec" > +- reg: Address and length of the control register area, followed by the > + address and length of the EEPROM holding the MAC address and > + microengine firmware > +- interrupts: Should contain ethernet controller interrupt > +- clocks: phandle to the PHY reference clock > +- clock-names: Should be "phy_ref_clk" If clock-names is mandatory now even when only a single clock is specified, you should add it to the example as well. However, please be aware that hardware has shipped now with DT images that specify a only a single clock and no clock-names property: those will require a firmware upgrade before they can use this version of the driver. > +- phy-mode: See ethernet.txt file in the same directory > +- phy-handle: See ethernet.txt in the same directory. > + > +- mdio device tree subnode: When the Netsec has a phy connected to its local > + mdio, there must be device tree subnode with the following > + required properties: > + > + - #address-cells: Must be <1>. > + - #size-cells: Must be <0>. > + > + For each phy on the mdio bus, there must be a node with the following > + fields: > + - compatible: Refer to phy.txt > + - reg: phy id used to communicate to phy. > + > +Optional properties: (See ethernet.txt file in the same directory) > +- dma-coherent: Boolean property, must only be present if memory > + accesses performed by the device are cache coherent. > +- local-mac-address: See ethernet.txt in the same directory. > +- mac-address: See ethernet.txt in the same directory. > +- max-speed: See ethernet.txt in the same directory. > +- max-frame-size: See ethernet.txt in the same directory. > + > +Example: > + eth0: ethernet@522d0000 { > + compatible = "socionext,synquacer-netsec"; > + reg = <0 0x522d0000 0x0 0x10000>, <0 0x10000000 0x0 0x10000>; > + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk_netsec>; > + phy-mode = "rgmii"; > + max-speed = <1000>; > + max-frame-size = <9000>; > + phy-handle = <&phy1>; > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + phy1: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + }; > + }; > + }; > -- > 2.7.4 >
Hi Ard, On Thu, Jan 4, 2018 at 3:07 AM, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote: > Hi Jassi, > > On 1 January 2018 at 05:14, <jassisinghbrar@gmail.com> wrote: >> From: Jassi Brar <jassisinghbrar@gmail.com> >> >> This patch adds documentation for Device-Tree bindings for the >> Socionext NetSec Controller driver. >> >> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> >> --- >> .../devicetree/bindings/net/socionext-netsec.txt | 53 ++++++++++++++++++++++ >> 1 file changed, 53 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/net/socionext-netsec.txt >> >> diff --git a/Documentation/devicetree/bindings/net/socionext-netsec.txt b/Documentation/devicetree/bindings/net/socionext-netsec.txt >> new file mode 100644 >> index 0000000..b70e35b >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/net/socionext-netsec.txt >> @@ -0,0 +1,53 @@ >> +* Socionext NetSec Ethernet Controller IP >> + >> +Required properties: >> +- compatible: Should be "socionext,synquacer-netsec" >> +- reg: Address and length of the control register area, followed by the >> + address and length of the EEPROM holding the MAC address and >> + microengine firmware >> +- interrupts: Should contain ethernet controller interrupt >> +- clocks: phandle to the PHY reference clock >> +- clock-names: Should be "phy_ref_clk" > > If clock-names is mandatory now even when only a single clock is > specified, > I know. Usually I follow maintainer's opinion unless I see myself losing sleep doing that. > you should add it to the example as well. > Done. Thanks > However, please > be aware that hardware has shipped now with DT images that specify a > only a single clock and no clock-names property: those will require a > firmware upgrade before they can use this version of the driver. > Ok, for now I have dared ignore clock-names in driver.... until we have to support again instance that take in more than one clock. Thanks.
diff --git a/Documentation/devicetree/bindings/net/socionext-netsec.txt b/Documentation/devicetree/bindings/net/socionext-netsec.txt new file mode 100644 index 0000000..b70e35b --- /dev/null +++ b/Documentation/devicetree/bindings/net/socionext-netsec.txt @@ -0,0 +1,53 @@ +* Socionext NetSec Ethernet Controller IP + +Required properties: +- compatible: Should be "socionext,synquacer-netsec" +- reg: Address and length of the control register area, followed by the + address and length of the EEPROM holding the MAC address and + microengine firmware +- interrupts: Should contain ethernet controller interrupt +- clocks: phandle to the PHY reference clock +- clock-names: Should be "phy_ref_clk" +- phy-mode: See ethernet.txt file in the same directory +- phy-handle: See ethernet.txt in the same directory. + +- mdio device tree subnode: When the Netsec has a phy connected to its local + mdio, there must be device tree subnode with the following + required properties: + + - #address-cells: Must be <1>. + - #size-cells: Must be <0>. + + For each phy on the mdio bus, there must be a node with the following + fields: + - compatible: Refer to phy.txt + - reg: phy id used to communicate to phy. + +Optional properties: (See ethernet.txt file in the same directory) +- dma-coherent: Boolean property, must only be present if memory + accesses performed by the device are cache coherent. +- local-mac-address: See ethernet.txt in the same directory. +- mac-address: See ethernet.txt in the same directory. +- max-speed: See ethernet.txt in the same directory. +- max-frame-size: See ethernet.txt in the same directory. + +Example: + eth0: ethernet@522d0000 { + compatible = "socionext,synquacer-netsec"; + reg = <0 0x522d0000 0x0 0x10000>, <0 0x10000000 0x0 0x10000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_netsec>; + phy-mode = "rgmii"; + max-speed = <1000>; + max-frame-size = <9000>; + phy-handle = <&phy1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; + };