diff mbox series

[34/38] target/hppa: Only use EXCP_DTLB_MISS

Message ID	20171229063145.29167-35-richard.henderson@linaro.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Thu, 28 Dec 2017 22:31:41 -0800 Message-Id: <20171229063145.29167-35-richard.henderson@linaro.org> In-Reply-To: <20171229063145.29167-1-richard.henderson@linaro.org> References: <20171229063145.29167-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH 34/38] target/hppa: Only use EXCP_DTLB_MISS Precedence: list Cc: deller@gmx.de Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	Add hppa-softmmu \| expand [00/38] Add hppa-softmmu [01/38] target/hppa: Skeleton support for hppa-softmmu [02/38] target/hppa: Define the rest of the PSW [03/38] target/hppa: Disable gateway page emulation for system mode [04/38] target/hppa: Define hardware exception types [05/38] target/hppa: Split address size from register size [06/38] target/hppa: Implement mmu_idx from IA privilege level [07/38] target/hppa: Implement the system mask instructions [08/38] target/hppa: Add space registers [09/38] target/hppa: Add control registers [10/38] target/hppa: Adjust insn mask for mfctl, w [11/38] target/hppa: Implement rfi [12/38] target/hppa: Fill in hppa_cpu_do_interrupt/hppa_cpu_exec_interrupt [13/38] target/hppa: Implement unaligned access trap [14/38] target/hppa: Use space registers in data operations [15/38] target/hppa: Do not set cs_base to iaoq_b [16/38] target/hppa: Avoid privilege level decrease during branches [17/38] target/hppa: Implement IASQ [18/38] target/hppa: Implement tlb_fill [19/38] target/hppa: Implement external interrupts [20/38] target/hppa: Implement the interval timer [21/38] target/hppa: Log unimplemented instructions [22/38] target/hppa: Implement ITLBA and ITLBP insns [23/38] target/hppa: Implement PTLB and PTLBE insns [24/38] target/hppa: Implement LDWA [25/38] target/hppa: Implement LPA [26/38] target/hppa: Implement LCI [27/38] target/hppa: Implement SYNCDMA insn [28/38] target/hppa: Implement a halt instruction [29/38] hw/hppa: Implement DINO system board [30/38] target/hppa: Optimize for flat addressing space [31/38] target/hppa: Add system registers to gdbstub [32/38] target/hppa: Add migration for the cpu [33/38] target/hppa: Implement B,GATE insn [34/38] target/hppa: Only use EXCP_DTLB_MISS [35/38] qom: Add MMU_DEBUG_LOAD [36/38] target/hppa: Use MMU_DEBUG_LOAD when reloading for CR[IIR] [37/38] target/hppa: Increase number of temp regs [38/38] target/hppa: Fix comment

Commit Message

Richard Henderson Dec. 29, 2017, 6:31 a.m. UTC

Unknown why this works, but if we return EXCP_ITLB_MISS we
will triple-fault the first userland instruction fetch.
Is it something to do with having a combined I/DTLB?

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/mem_helper.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index e2f94faab5..a0a385cb54 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -97,7 +97,9 @@  int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
     if (ent == NULL || !ent->entry_valid) {
         phys = 0;
         prot = 0;
-        ret = (ifetch ? EXCP_ITLB_MISS : EXCP_DTLB_MISS);
+        /* ??? Unconditionally report data tlb miss,
+           even if this is an instruction fetch.  */
+        ret = EXCP_DTLB_MISS;
         goto egress;
     }