From patchwork Thu Dec 28 22:41:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans de Goede X-Patchwork-Id: 853584 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3z74TC0PlGz9s75 for ; Fri, 29 Dec 2017 09:41:35 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751110AbdL1Wlc (ORCPT ); Thu, 28 Dec 2017 17:41:32 -0500 Received: from mx1.redhat.com ([209.132.183.28]:33526 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750982AbdL1Wlc (ORCPT ); Thu, 28 Dec 2017 17:41:32 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id D5D5E4A6FF; Thu, 28 Dec 2017 22:41:31 +0000 (UTC) Received: from shalem.localdomain.com (ovpn-116-51.ams2.redhat.com [10.36.116.51]) by smtp.corp.redhat.com (Postfix) with ESMTP id 73FC45D9C7; Thu, 28 Dec 2017 22:41:30 +0000 (UTC) From: Hans de Goede To: Mika Westerberg , Heikki Krogerus , Linus Walleij Cc: Hans de Goede , Andy Shevchenko , linux-gpio@vger.kernel.org Subject: [PATCH] pinctrl: baytrail: Enable glitch filter on some systems Date: Thu, 28 Dec 2017 23:41:28 +0100 Message-Id: <20171228224128.29065-1-hdegoede@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Thu, 28 Dec 2017 22:41:31 +0000 (UTC) Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On some systems, some PCB traces attached to edge triggered GpioInts are routed in such a way that they pick up enough interference to constantly (many times per second) trigger. Enabling glitch-filtering fixes this. This commit introduces a DMI list with systems which need this, but maybe we should enable this on all Bay Trail GPIOs used as edge-triggered interrupts? Signed-off-by: Hans de Goede --- I wonder if Windows just enables glitch-filtering on all GPIOs? Can someone perhaps dump the register at physical address 0xFED0C550 (SATAGP0 PINCONF) on a Bay Trail system using GPIO attached volume buttons while running Windows? --- drivers/pinctrl/intel/pinctrl-baytrail.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 9c1ca29c60b7..21a60b5dac57 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -14,6 +14,7 @@ * more details. */ +#include #include #include #include @@ -46,6 +47,7 @@ #define BYT_TRIG_POS BIT(25) #define BYT_TRIG_LVL BIT(24) #define BYT_DEBOUNCE_EN BIT(20) +#define BYT_GLITCH_FILTER_EN BIT(19) #define BYT_PULL_STR_SHIFT 9 #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT) #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) @@ -205,6 +207,7 @@ struct byt_gpio { const struct byt_pinctrl_soc_data *soc_data; struct byt_community *communities_copy; struct byt_gpio_pin_context *saved_context; + bool enable_glitch_filter; }; /* SCORE pins, aka GPIOC_ or GPIO_S0_SC[] */ @@ -1580,6 +1583,9 @@ static int byt_irq_type(struct irq_data *d, unsigned int type) value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); + if ((type & IRQ_TYPE_EDGE_BOTH) && vg->enable_glitch_filter) + value |= BYT_GLITCH_FILTER_EN; + writel(value, reg); if (type & IRQ_TYPE_EDGE_BOTH) @@ -1776,6 +1782,19 @@ static const struct acpi_device_id byt_gpio_acpi_match[] = { }; MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match); +/* Some devices need the glitch filter on edge interrupts to avoid IRQ storms */ +static const struct dmi_system_id enable_glitch_filter_list[] = { + { + /* GP-electronic T701 */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Insyde"), + DMI_MATCH(DMI_PRODUCT_NAME, "T701"), + DMI_MATCH(DMI_BIOS_VERSION, "BYT70A.YNCHENG.WIN.007"), + }, + }, + {} +}; + static int byt_pinctrl_probe(struct platform_device *pdev) { const struct byt_pinctrl_soc_data *soc_data = NULL; @@ -1816,6 +1835,9 @@ static int byt_pinctrl_probe(struct platform_device *pdev) return ret; } + if (dmi_check_system(enable_glitch_filter_list)) + vg->enable_glitch_filter = true; + vg->pctl_desc = byt_pinctrl_desc; vg->pctl_desc.name = dev_name(&pdev->dev); vg->pctl_desc.pins = vg->soc_data->pins;