Patchwork [U-Boot,v2,1/2] powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers

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Submitter York Sun
Date March 2, 2011, 7:46 p.m.
Message ID <1299095182-17433-1-git-send-email-yorksun@freescale.com>
Download mbox | patch
Permalink /patch/85131/
State Superseded
Delegated to: Kumar Gala
Headers show

Comments

York Sun - March 2, 2011, 7:46 p.m.
The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |   28 ++++++++++++++++++++++++----
 1 files changed, 24 insertions(+), 4 deletions(-)

Patch

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 41bad35..d8e9142 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -371,6 +371,21 @@  static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 
 	refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
 	wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
+
+	switch (wrrec_mclk) { /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
+	case 9:
+		wrrec_mclk = 10;
+		break;
+	case 11:
+		wrrec_mclk = 12;
+		break;
+	case 13:
+		wrrec_mclk = 14;
+		break;
+	case 15:
+		wrrec_mclk = 16;
+		break;
+	}
 	if (popts->OTF_burst_chop_en)
 		wrrec_mclk += 2;
 
@@ -854,12 +869,17 @@  static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 	 */
 	dll_on = 1;
 	wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
-	if (wr_mclk >= 12)
-		wr = 6;
+	if (wr_mclk >= 15)
+		wr = 0;	/* 16 cycles */
+	else if (wr_mclk >= 13)
+		wr = 7;	/* 14 cycles */
+	else if (wr_mclk >= 11)
+		wr = 6;	/* 12 cycles */
 	else if (wr_mclk >= 9)
-		wr = 5;
+		wr = 5;		/* 10 cycles */
 	else
-		wr = wr_mclk - 4;
+		wr = wr_mclk - 4;	/* 5~8 cycles */
+
 	dll_rst = 0;	/* dll no reset */
 	mode = 0;	/* normal mode */