| Message ID | 20171219232940.659-3-niklas.cassel@axis.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support | expand |
Hi, Às 11:29 PM de 12/19/2017, Niklas Cassel escreveu: > Previously, dw_pcie_ep_set_msi() wrote all bits in the Message Control > register, thus overwriting the PCI_MSI_FLAGS_64BIT bit. > By clearing the PCI_MSI_FLAGS_64BIT bit, we break MSI > on systems where the RC has set a 64 bit MSI address. > Fix dw_pcie_ep_set_msi() so that it only sets MMC bits. > > Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> > --- > drivers/pci/dwc/pcie-designware-ep.c | 4 +++- > drivers/pci/dwc/pcie-designware.h | 1 + > 2 files changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c > index d53d5f168363..c92ab87fd660 100644 > --- a/drivers/pci/dwc/pcie-designware-ep.c > +++ b/drivers/pci/dwc/pcie-designware-ep.c > @@ -220,7 +220,9 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int) > struct dw_pcie_ep *ep = epc_get_drvdata(epc); > struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > > - val = (encode_int << MSI_CAP_MMC_SHIFT); > + val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); > + val &= ~MSI_CAP_MMC_MASK; > + val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK; > dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val); > > return 0; > diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h > index ecdede68522a..9aaf0cd04dd6 100644 > --- a/drivers/pci/dwc/pcie-designware.h > +++ b/drivers/pci/dwc/pcie-designware.h > @@ -101,6 +101,7 @@ > > #define MSI_MESSAGE_CONTROL 0x52 > #define MSI_CAP_MMC_SHIFT 1 > +#define MSI_CAP_MMC_MASK (7 << MSI_CAP_MMC_SHIFT) > #define MSI_CAP_MME_SHIFT 4 > #define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT) > #define MSI_MESSAGE_ADDR_L32 0x54 > Acked-by: Joao Pinto <jpinto@synopsys.com>
On Wednesday, December 20, 2017 2:18 PM, Joao Pinto wrote: > > Hi, > > Às 11:29 PM de 12/19/2017, Niklas Cassel escreveu: > > Previously, dw_pcie_ep_set_msi() wrote all bits in the Message Control > > register, thus overwriting the PCI_MSI_FLAGS_64BIT bit. > > By clearing the PCI_MSI_FLAGS_64BIT bit, we break MSI > > on systems where the RC has set a 64 bit MSI address. > > Fix dw_pcie_ep_set_msi() so that it only sets MMC bits. > > > > Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> > > --- > > drivers/pci/dwc/pcie-designware-ep.c | 4 +++- > > drivers/pci/dwc/pcie-designware.h | 1 + > > 2 files changed, 4 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pci/dwc/pcie-designware-ep.c > b/drivers/pci/dwc/pcie-designware-ep.c > > index d53d5f168363..c92ab87fd660 100644 > > --- a/drivers/pci/dwc/pcie-designware-ep.c > > +++ b/drivers/pci/dwc/pcie-designware-ep.c > > @@ -220,7 +220,9 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, > u8 encode_int) > > struct dw_pcie_ep *ep = epc_get_drvdata(epc); > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > > > > - val = (encode_int << MSI_CAP_MMC_SHIFT); > > + val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); > > + val &= ~MSI_CAP_MMC_MASK; > > + val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK; > > dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val); > > > > return 0; > > diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie- > designware.h > > index ecdede68522a..9aaf0cd04dd6 100644 > > --- a/drivers/pci/dwc/pcie-designware.h > > +++ b/drivers/pci/dwc/pcie-designware.h > > @@ -101,6 +101,7 @@ > > > > #define MSI_MESSAGE_CONTROL 0x52 > > #define MSI_CAP_MMC_SHIFT 1 > > +#define MSI_CAP_MMC_MASK (7 << MSI_CAP_MMC_SHIFT) > > #define MSI_CAP_MME_SHIFT 4 > > #define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT) > > #define MSI_MESSAGE_ADDR_L32 0x54 > > > > Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Best regards, Jingoo Han
diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c index d53d5f168363..c92ab87fd660 100644 --- a/drivers/pci/dwc/pcie-designware-ep.c +++ b/drivers/pci/dwc/pcie-designware-ep.c @@ -220,7 +220,9 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int) struct dw_pcie_ep *ep = epc_get_drvdata(epc); struct dw_pcie *pci = to_dw_pcie_from_ep(ep); - val = (encode_int << MSI_CAP_MMC_SHIFT); + val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); + val &= ~MSI_CAP_MMC_MASK; + val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK; dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val); return 0; diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h index ecdede68522a..9aaf0cd04dd6 100644 --- a/drivers/pci/dwc/pcie-designware.h +++ b/drivers/pci/dwc/pcie-designware.h @@ -101,6 +101,7 @@ #define MSI_MESSAGE_CONTROL 0x52 #define MSI_CAP_MMC_SHIFT 1 +#define MSI_CAP_MMC_MASK (7 << MSI_CAP_MMC_SHIFT) #define MSI_CAP_MME_SHIFT 4 #define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT) #define MSI_MESSAGE_ADDR_L32 0x54
Previously, dw_pcie_ep_set_msi() wrote all bits in the Message Control register, thus overwriting the PCI_MSI_FLAGS_64BIT bit. By clearing the PCI_MSI_FLAGS_64BIT bit, we break MSI on systems where the RC has set a 64 bit MSI address. Fix dw_pcie_ep_set_msi() so that it only sets MMC bits. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> --- drivers/pci/dwc/pcie-designware-ep.c | 4 +++- drivers/pci/dwc/pcie-designware.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-)