From patchwork Tue Dec 19 09:31:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 850734 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="XlkSPslo"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3z1CP24xj6z9s82 for ; Tue, 19 Dec 2017 20:32:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966790AbdLSJcg (ORCPT ); Tue, 19 Dec 2017 04:32:36 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:15660 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932971AbdLSJc2 (ORCPT ); Tue, 19 Dec 2017 04:32:28 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBJ9VoG5030820; Tue, 19 Dec 2017 03:31:50 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513675910; bh=sxGvI5O1JpQQsebqrxB/n5iwZatgZP2abKeKglZPFR0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=XlkSPslo9OjJXY+w0ExnVDUMPCPIIZdzqxhX2us0FPAeve/f9gXNb3D7fhFg+8lFp tFvHAiMRfsR/JF+gHbQ1Eb4moJMSdNdz6gysDMi9HPbAXpDTeZu0z3tr2w+PY0y+f3 DhIbrY+ZuZwWGLkiT7WaslTm/ENGsb4Xti9Qn3Ak= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9Vovi015295; Tue, 19 Dec 2017 03:31:50 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 19 Dec 2017 03:31:49 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 19 Dec 2017 03:31:49 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9VgHu012627; Tue, 19 Dec 2017 03:31:46 -0600 From: Kishon Vijay Abraham I To: Tony Lindgren , CC: Rob Herring , Mark Rutland , Russell King , , , , , , , Subject: [PATCH 1/7] ARM: dts: dra7: Add properties to enable PCIe x2 lane mode Date: Tue, 19 Dec 2017 15:01:27 +0530 Message-ID: <20171219093133.16565-2-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171219093133.16565-1-kishon@ti.com> References: <20171219093133.16565-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable PCIe x2 lane mode are added here. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/dra7.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index ac9216293b7c..9966d82dbd7c 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -309,6 +309,8 @@ ti,hwmods = "pcie1"; phys = <&pcie1_phy>; phy-names = "pcie-phy0"; + ti,syscon-lane-conf = <&scm_conf 0x558>; + ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie1_intc 1>, <0 0 0 2 &pcie1_intc 2>, @@ -334,6 +336,8 @@ phys = <&pcie1_phy>; phy-names = "pcie-phy0"; ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; + ti,syscon-lane-conf = <&scm_conf 0x558>; + ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; status = "disabled"; }; };