| Message ID | 1513621711-7976-2-git-send-email-sakar.arora@arm.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | None | expand |
On 2017-12-19 02:28 AM, Sakar Arora wrote: > SBBR spec requires SPCR table to describe GSIV based > interrupt number for UART. > Some ARM server implementations set interrupt > type as IOAPIC, which is a valid type for GSIV > based interrupt. > > Signed-off-by: Sakar Arora <sakar.arora@arm.com> > --- > src/acpi/spcr/spcr.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/src/acpi/spcr/spcr.c b/src/acpi/spcr/spcr.c > index 2f37e3f..740d569 100644 > --- a/src/acpi/spcr/spcr.c > +++ b/src/acpi/spcr/spcr.c > @@ -74,9 +74,11 @@ static int spcr_sbbr_gsiv_test(fwts_framework *fw) > { > if (fw->flags & FWTS_FLAG_TEST_SBBR) { > const uint8_t ARMH_GIC_INTR_MASK = 0x08; > + const uint8_t IO_APIC_INTR_MASK = 0x02; > > - if ( (spcr->interrupt_type == ARMH_GIC_INTR_MASK) && > - (spcr->gsi != 0x0000000000000000) ) > + if ((spcr->interrupt_type == ARMH_GIC_INTR_MASK || > + spcr->interrupt_type == IO_APIC_INTR_MASK) && > + spcr->gsi != 0x0) > fwts_passed(fw, "SPCR appears to be populated with correct GSIV interrupt" > "routing information for ARM PL011 UART Device"); > else > Acked-by: Alex Hung <alex.hung@canonical.com>
On 12/19/2017 02:28 AM, Sakar Arora wrote: > SBBR spec requires SPCR table to describe GSIV based > interrupt number for UART. > Some ARM server implementations set interrupt > type as IOAPIC, which is a valid type for GSIV > based interrupt. > > Signed-off-by: Sakar Arora <sakar.arora@arm.com> > --- > src/acpi/spcr/spcr.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/src/acpi/spcr/spcr.c b/src/acpi/spcr/spcr.c > index 2f37e3f..740d569 100644 > --- a/src/acpi/spcr/spcr.c > +++ b/src/acpi/spcr/spcr.c > @@ -74,9 +74,11 @@ static int spcr_sbbr_gsiv_test(fwts_framework *fw) > { > if (fw->flags & FWTS_FLAG_TEST_SBBR) { > const uint8_t ARMH_GIC_INTR_MASK = 0x08; > + const uint8_t IO_APIC_INTR_MASK = 0x02; > > - if ( (spcr->interrupt_type == ARMH_GIC_INTR_MASK) && > - (spcr->gsi != 0x0000000000000000) ) > + if ((spcr->interrupt_type == ARMH_GIC_INTR_MASK || > + spcr->interrupt_type == IO_APIC_INTR_MASK) && > + spcr->gsi != 0x0) > fwts_passed(fw, "SPCR appears to be populated with correct GSIV interrupt" > "routing information for ARM PL011 UART Device"); > else Acked-by: Ivan Hu <ivan.hu@canonical.com>
diff --git a/src/acpi/spcr/spcr.c b/src/acpi/spcr/spcr.c index 2f37e3f..740d569 100644 --- a/src/acpi/spcr/spcr.c +++ b/src/acpi/spcr/spcr.c @@ -74,9 +74,11 @@ static int spcr_sbbr_gsiv_test(fwts_framework *fw) { if (fw->flags & FWTS_FLAG_TEST_SBBR) { const uint8_t ARMH_GIC_INTR_MASK = 0x08; + const uint8_t IO_APIC_INTR_MASK = 0x02; - if ( (spcr->interrupt_type == ARMH_GIC_INTR_MASK) && - (spcr->gsi != 0x0000000000000000) ) + if ((spcr->interrupt_type == ARMH_GIC_INTR_MASK || + spcr->interrupt_type == IO_APIC_INTR_MASK) && + spcr->gsi != 0x0) fwts_passed(fw, "SPCR appears to be populated with correct GSIV interrupt" "routing information for ARM PL011 UART Device"); else
SBBR spec requires SPCR table to describe GSIV based interrupt number for UART. Some ARM server implementations set interrupt type as IOAPIC, which is a valid type for GSIV based interrupt. Signed-off-by: Sakar Arora <sakar.arora@arm.com> --- src/acpi/spcr/spcr.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)