From patchwork Mon Dec 18 18:11:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mahesh J Salgaonkar X-Patchwork-Id: 850277 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3z0q391fQZz9sNr for ; Tue, 19 Dec 2017 05:15:49 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3z0q385VKvzDrSR for ; Tue, 19 Dec 2017 05:15:48 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=mahesh@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3z0py73jrNzDrfp for ; Tue, 19 Dec 2017 05:11:27 +1100 (AEDT) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id vBII7EKe088509 for ; Mon, 18 Dec 2017 13:11:23 -0500 Received: from e06smtp12.uk.ibm.com (e06smtp12.uk.ibm.com [195.75.94.108]) by mx0a-001b2d01.pphosted.com with ESMTP id 2exhuk2e33-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 18 Dec 2017 13:11:23 -0500 Received: from localhost by e06smtp12.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 18 Dec 2017 18:11:17 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id vBIIBHD260555388; Mon, 18 Dec 2017 18:11:17 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9044C11C052; Mon, 18 Dec 2017 18:05:31 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6F06811C04C; Mon, 18 Dec 2017 18:05:30 +0000 (GMT) Received: from jupiter.in.ibm.com (unknown [9.85.73.50]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 18 Dec 2017 18:05:30 +0000 (GMT) From: Mahesh J Salgaonkar To: skiboot list Date: Mon, 18 Dec 2017 23:41:15 +0530 User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 17121818-0008-0000-0000-000004B87020 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17121818-0009-0000-0000-00001E4B8D99 Message-Id: <151362060219.27708.7450373707409056345.stgit@jupiter.in.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-12-18_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1712180240 Subject: [Skiboot] [PATCH v2] opal/xstop: Use nvram option to enable/disable sw checkstop. X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Mahesh Salgaonkar Add a mechanism to enable/disable sw checkstop by looking at nvram option opal-sw-xstop=. For now this patch disables the sw checkstop trigger unless explicitly enabled through nvram option 'opal-sw-xstop=enable'i for p9. This will allow an opportunity to get host kernel in panic path or xmon for unrecoverable HMIs or MCE, to be able to debug the issue effectively. To enable sw checkstop in opal issue following command: # nvram -p ibm,skiboot --update-config opal-sw-xstop=enable NOTE: This is a workaround patch to disable sw checkstop by default to gain control in host kernel for better checkstop debugging. Once we have most of the checkstop issues stabilized/resolved, revisit this patch to enable sw checkstop by default. For p8 platform it will remain enabled by default unless explicitly disabled. To disable sw checkstop on p8 issue following command: # nvram -p ibm,skiboot --update-config opal-sw-xstop=disable Signed-off-by: Mahesh Salgaonkar Reviewed-by: Balbir Singh --- Change in v2: - Add pr_log to indicate that sw checkstop was disabled. --- hw/xscom.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/hw/xscom.c b/hw/xscom.c index de5a27e..0501278 100644 --- a/hw/xscom.c +++ b/hw/xscom.c @@ -24,6 +24,7 @@ #include #include #include +#include /* Mask of bits to clear in HMER before an access */ #define HMER_CLR_MASK (~(SPR_HMER_XSCOM_FAIL | \ @@ -826,6 +827,37 @@ static void xscom_init_chip_info(struct proc_chip *chip) int64_t xscom_trigger_xstop(void) { int rc = OPAL_UNSUPPORTED; + bool xstop_disabled = false; + + /* + * Workaround until we iron out all checkstop issues at present. + * + * For p9: + * By default do not trigger sw checkstop unless explicitly enabled + * through nvram option 'opal-sw-xstop=enable'. + * + * For p8: + * Keep it enabled by default unless explicitly disabled. + * + * NOTE: Once all checkstop issues are resolved/stabilized reverse + * the logic to enable sw checkstop by default on p9. + */ + switch (proc_gen) { + case proc_gen_p8: + if (nvram_query_eq("opal-sw-xstop", "disable")) + xstop_disabled = true; + break; + case proc_gen_p9: + default: + if (!nvram_query_eq("opal-sw-xstop", "enable")) + xstop_disabled = true; + break; + } + + if (xstop_disabled) { + prlog(PR_NOTICE, "Software initiated checkstop disabled.\n"); + return rc; + } if (xstop_xscom.addr) rc = xscom_writeme(xstop_xscom.addr,