From patchwork Tue Mar 1 23:22:15 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pat Haugen X-Patchwork-Id: 85011 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id E8998B7146 for ; Wed, 2 Mar 2011 10:22:31 +1100 (EST) Received: (qmail 12901 invoked by alias); 1 Mar 2011 23:22:27 -0000 Received: (qmail 12893 invoked by uid 22791); 1 Mar 2011 23:22:26 -0000 X-SWARE-Spam-Status: No, hits=-1.4 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from e31.co.us.ibm.com (HELO e31.co.us.ibm.com) (32.97.110.149) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 01 Mar 2011 23:22:21 +0000 Received: from d03relay02.boulder.ibm.com (d03relay02.boulder.ibm.com [9.17.195.227]) by e31.co.us.ibm.com (8.14.4/8.13.1) with ESMTP id p21N7JpS008685 for ; Tue, 1 Mar 2011 16:07:19 -0700 Received: from d03av02.boulder.ibm.com (d03av02.boulder.ibm.com [9.17.195.168]) by d03relay02.boulder.ibm.com (8.13.8/8.13.8/NCO v9.1) with ESMTP id p21NMHpq119152 for ; Tue, 1 Mar 2011 16:22:17 -0700 Received: from d03av02.boulder.ibm.com (loopback [127.0.0.1]) by d03av02.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p21NMHiL019625 for ; Tue, 1 Mar 2011 16:22:17 -0700 Received: from pthw510.rchland.ibm.com (sig-9-65-68-113.mts.ibm.com [9.65.68.113]) by d03av02.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id p21NMGnU019201; Tue, 1 Mar 2011 16:22:16 -0700 Message-ID: <4D6D7FA7.2010306@linux.vnet.ibm.com> Date: Tue, 01 Mar 2011 17:22:15 -0600 From: Pat Haugen User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org CC: Vladimir Makarov , Jeff Law Subject: [PATCH RFC] PR 47862: Fix caller-save spill of vectors on PowerPC X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org PR47862 documents a problem where we are only saving/restoring half of a vector across a call on PowerPC. The lower 32 VSX vector regs (vs0..vs31) overlap the legacy floating point registers (F0..F31), but are 16 bytes long instead of 8 (FP reg overlaps dword0 of corresponding vector reg). The code in caller-save.c:init_caller_save() sets up the mode for all caller-save regs without regard to what mode is actually in the register at the time of spill. Currently DI mode is picked for the floating point regs which leads to only saving/restoring half the vector (dword0). The following patch defines HARD_REGNO_CALLER_SAVE_MODE so that it will return V2DF mode for the FP regs for TARGET_VSX. This fixes the issue, but I believe has the undesirable effect of causing all FP regs to now be save/restored with 16-byte vector store/load insns, even if they are only holding scalar floating point values. Besides wasting stack space for scalar values, using the vector insns can also affect performance due to pipeline/resource constraints. Are there alternative solutions to this such that we'll use scalar FP store/load insns for SF/DF mode spill and vector store/load insns for vector spill? Or is the following a correct start on the patch, but more needs to be done to setup_save_area() and/or save_call_clobbered_regs() to emit the appropriate insns based on mode being spilled (this seems like it could be some non-trivial rip up)? Any comments appreciated. -Pat Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h (revision 170438) +++ gcc/config/rs6000/rs6000.h (working copy) @@ -1005,6 +1005,12 @@ extern unsigned rs6000_pointer_size; #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)] +/* Ensure vector modes are handled correctly in FP regs for VSX */ +#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ + (TARGET_VSX && FP_REGNO_P (REGNO) \ + ? V2DFmode \ + : choose_hard_reg_mode ((REGNO), (NREGS), false)) + #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ (((TARGET_32BIT && TARGET_POWERPC64 \ && (GET_MODE_SIZE (MODE) > 4) \