[v2,1/3] i2c: piix4: Fix SMBus port selection for AMD Family 16h chips

Message ID 3f87f37117e6662661f16ea8fdbbdffff5d2e414.1513215039.git.andrew.cooks@opengear.com
State Superseded
Headers show
Series
  • Enable ACPI-defined peripherals on i2c-piix4 SMBus
Related show

Commit Message

Andrew Cooks Dec. 14, 2017, 3:11 a.m.
HUDSON2 SMBus controller has the same port selection register as
described and fixed in commit 0fe16195f89173652cf111d7b384941b00c5aabd
("i2c: piix4: Fix SMBus port selection for AMD Family 17h chips")

The SMBus port selection register is common to multiple Families and
models, as documented in AMD's publicly available BIOS and Kernel
Developer Guides:

 - 50742 -- Family 15h Model 60h-6Fh (PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)
 - 55072 -- Family 15h Model 70h-7Fh (PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)
 - 52740 -- Family 16h Model 30h-3Fh (PCI_DEVICE_ID_AMD_HUDSON2_SMBUS)

The following additional public AMD BKDG documents were checked and do
not share the same port selection register:

 - 42301 -- Family 15h Model 00h-0Fh doesn't mention any
 - 42300 -- Family 15h Model 10h-1Fh doesn't mention any
 - 49125 -- Family 15h Model 30h-3Fh doesn't mention any

 - 48751 -- Family 16h Model 00h-0Fh uses the previously supported
   index register SB800_PIIX4_PORT_IDX_ALT at 0x2e

Signed-off-by: Andrew Cooks <andrew.cooks@opengear.com>
---
 drivers/i2c/busses/i2c-piix4.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Andrew Cooks Dec. 14, 2017, 11:58 p.m. | #1
Hi Jean

On 14/12/17 13:11, Andrew Cooks wrote:
> HUDSON2 SMBus controller has the same port selection register as
> described and fixed in commit 0fe16195f89173652cf111d7b384941b00c5aabd
> ("i2c: piix4: Fix SMBus port selection for AMD Family 17h chips")
> 
> The SMBus port selection register is common to multiple Families and
> models, as documented in AMD's publicly available BIOS and Kernel
> Developer Guides:
> 
>  - 50742 -- Family 15h Model 60h-6Fh (PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)
>  - 55072 -- Family 15h Model 70h-7Fh (PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)
>  - 52740 -- Family 16h Model 30h-3Fh (PCI_DEVICE_ID_AMD_HUDSON2_SMBUS)
> 
> The following additional public AMD BKDG documents were checked and do
> not share the same port selection register:
> 
>  - 42301 -- Family 15h Model 00h-0Fh doesn't mention any
>  - 42300 -- Family 15h Model 10h-1Fh doesn't mention any
>  - 49125 -- Family 15h Model 30h-3Fh doesn't mention any
> 
>  - 48751 -- Family 16h Model 00h-0Fh uses the previously supported
>    index register SB800_PIIX4_PORT_IDX_ALT at 0x2e

I just noticed that commit 6befa3fde65fe437f588da490c07a114393ce229 ("i2c: piix4: Support alternative port selection register") also fixed the port selection for Hudson2, and this patch is incorrect. Unfortunately the AMD naming and PCI Device IDs aren't particularly helpful here.

In both the 51192 Bolton Register Reference Guide[1] and 52740 BKDG for Family 16h Model 30h-3Fh[2], the PCI Device ID for the SMBus controller is 0x780b, but the location of the SmBus0Sel port selection bits are different.

We might be able to distinguish between them using the Revision ID in PCI register 0x08 (in addition to the PCI Device ID, of course).

  Bolton [1] is Revision 0x15
  Family 16h Model 30h (Hudson2?)[2] is Revision 0x1F
  Family 15h Model 70h [3] uses 0x4A
  Family 15h Model 60h [4] uses 0x4A

Thoughts?


Andrew


[1] http://support.amd.com/TechDocs/51192_Bolton_FCH_RRG.pdf
[2] http://support.amd.com/TechDocs/52740_16h_Models_30h-3Fh_BKDG.pdf
[3] http://support.amd.com/TechDocs/55072_AMD_Family_15h_Models_70h-7Fh_BKDG.pdf
[4] http://support.amd.com/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf

Patch

diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c
index 462948e..b92ea5d 100644
--- a/drivers/i2c/busses/i2c-piix4.c
+++ b/drivers/i2c/busses/i2c-piix4.c
@@ -99,7 +99,7 @@ 
 #define SB800_PIIX4_PORT_IDX_MASK	0x06
 #define SB800_PIIX4_PORT_IDX_SHIFT	1
 
-/* On kerncz, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
+/* On kerncz and Hudson2, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
 #define SB800_PIIX4_PORT_IDX_KERNCZ		0x02
 #define SB800_PIIX4_PORT_IDX_MASK_KERNCZ	0x18
 #define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ	3
@@ -360,12 +360,12 @@  static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
 	/* Find which register is used for port selection */
 	if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD) {
 		switch (PIIX4_dev->device) {
+		case PCI_DEVICE_ID_AMD_HUDSON2_SMBUS:
 		case PCI_DEVICE_ID_AMD_KERNCZ_SMBUS:
 			piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ;
 			piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ;
 			piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ;
 			break;
-		case PCI_DEVICE_ID_AMD_HUDSON2_SMBUS:
 		default:
 			piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT;
 			piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;