From patchwork Wed Dec 13 09:33:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 847909 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-469101-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="OopBxB0v"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yxWj65s0hz9sBZ for ; Wed, 13 Dec 2017 20:33:42 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:to:cc:subject:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=R45Brpifc+rP82zT IPCjhYnQXMuPQsJ9hf1udQ6HZomeMgo7jxRCsDee1wb1DyLGuiQbjor1hjDTiahG 8NvAvDXe/7I5i/zKjHjU0FhnUJII18bHBk132tswJPjITJ/UClqXfKqCOdHqxuSt 2zk7WR8c9SANngQO0AaftHVhaHk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:to:cc:subject:mime-version:content-type :content-transfer-encoding; s=default; bh=y2X2c7YxLEwvler244BSMP PnegM=; b=OopBxB0vv5dKTGgo1mPI56oBQn4x3uIB9Wtkm9gxLBVguqxM20nuU+ 6Rt1eWZkALAto6chJlwMZBVueybNHZq7mOCHGNbXn6XDhdbqJWWqGpXrkoOoYUvE aVo90SrCOut28/mtLLx3neBNA9biwfCopGjXLtlE8qy6/f7bkLgpY= Received: (qmail 90605 invoked by alias); 13 Dec 2017 09:33:32 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 83100 invoked by uid 89); 13 Dec 2017 09:33:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.2 spammy=puzzled X-HELO: prv-mh.provo.novell.com Received: from prv-mh.provo.novell.com (HELO prv-mh.provo.novell.com) (137.65.248.74) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 13 Dec 2017 09:33:27 +0000 Received: from INET-PRV-MTA by prv-mh.provo.novell.com with Novell_GroupWise; Wed, 13 Dec 2017 02:33:25 -0700 Message-Id: <5A3101F40200007800197102@prv-mh.provo.novell.com> Date: Wed, 13 Dec 2017 02:33:24 -0700 From: "Jan Beulich" To: Cc: "Kirill Yukhin" , , Subject: [PATCH] x86: don't use AVX512BW vmovdqu variants without -mavx512bw Mime-Version: 1.0 Content-Disposition: inline Simply mirror the MODE_XI logic of handling unaligned operands in mov_internal into MODE_TI / MODE_OI handling. gcc/ 2017-12-13 Jan Beulich * sse.md (mov_internal): Tighten condition for when to use vmovdqu for TI and OI modes. gcc/testsuite/ 2017-12-13 Jan Beulich * gcc.target/i386/avx512vl-no-vmovdqu8.c, gcc.target/i386/avx512vl-no-vmovdqu16.c: New. --- I'm also being puzzled by the code being generated for the 256-bit cases (which shouldn't differ much from the 128-bit ones). --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1005,8 +1005,14 @@ case MODE_TI: if (misaligned_operand (operands[0], mode) || misaligned_operand (operands[1], mode)) - return TARGET_AVX512VL ? "vmovdqu\t{%1, %0|%0, %1}" - : "%vmovdqu\t{%1, %0|%0, %1}"; + return TARGET_AVX512VL + && (mode == V4SImode + || mode == V2DImode + || mode == V8SImode + || mode == V4DImode + || TARGET_AVX512BW) + ? "vmovdqu\t{%1, %0|%0, %1}" + : "%vmovdqu\t{%1, %0|%0, %1}"; else return TARGET_AVX512VL ? "vmovdqa64\t{%1, %0|%0, %1}" : "%vmovdqa\t{%1, %0|%0, %1}"; --- a/gcc/testsuite/gcc.target/i386/avx512vl-no-vmovdqu16.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-no-vmovdqu16.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512vl -mno-avx512bw" } */ + +typedef unsigned int __attribute__((mode(HI), vector_size(16))) v8hi_t; +typedef unsigned int __attribute__((mode(HI), vector_size(32))) v16hi_t; + +struct s8hi { + int i; + v8hi_t __attribute__((packed)) v; +}; +struct s16hi { + int i; + v16hi_t __attribute__((packed)) v; +}; + +void f8hi(struct s8hi*p1, const struct s8hi*p2) { + p1->v += p2->v; +} + +void f16hi(struct s16hi*p1, const struct s16hi*p2) { + p1->v += p2->v; +} + +/* { dg-final { scan-assembler-not "^\[ \t\]*vmovdq\[au\](8|16)" } } */ --- a/gcc/testsuite/gcc.target/i386/avx512vl-no-vmovdqu8.c +++ b/gcc/testsuite/gcc.target/i386/avx512vl-no-vmovdqu8.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512vl -mno-avx512bw" } */ + +typedef unsigned int __attribute__((mode(QI), vector_size(16))) v16qi_t; +typedef unsigned int __attribute__((mode(QI), vector_size(32))) v32qi_t; + +struct s16qi { + int i; + v16qi_t __attribute__((packed)) v; +}; +struct s32qi { + int i; + v32qi_t __attribute__((packed)) v; +}; + +void f16qi(struct s16qi*p1, const struct s16qi*p2) { + p1->v += p2->v; +} + +void f32qi(struct s32qi*p1, const struct s32qi*p2) { + p1->v += p2->v; +} + +/* { dg-final { scan-assembler-not "^\[ \t\]*vmovdq\[au\](8|16)" } } */